A unified approach to constrained mapping and routing on network-on-chip architectures. - Andreas Hansson 001; Kees Goossens; Andrei Radulescu (CODES+ISSS, 2005)

Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip. - Andreas Hansson 001; Martijn Coenen; Kees Goossens (CODES+ISSS, 2007)

Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip. - Andreas Hansson 001; Martijn Coenen; Kees Goossens (DATE, 2007)

Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip. - Akash Kumar 001; Andreas Hansson 001; Jos Huisken; Henk Corporaal (DATE, 2007)

Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases. - Andreas Hansson 001; Kees Goossens (NOCS, 2007)

Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip. - Andreas Hansson 001; Kees Goossens; Andrei Radulescu (VLSI Design, 2007)

A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic. - Andreas Hansson 001; Kees Goossens; Andrei Radulescu (VLSI Design, 2007)

Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip. - Andreas Hansson 001; Maarten Wiggers; Arno Moonen; Kees Goossens; Marco Bekooij (NOCS, 2008)

A monitoring-aware network-on-chip design flow. - Calin Ciordas; Andreas Hansson 001; Kees Goossens; Twan Basten (J. Syst. Archit., 2008)

An on-chip interconnect and protocol stack for multiple communication paradigms and programming models. - Andreas Hansson 001; Kees Goossens (CODES+ISSS, 2009)

Aelite: A flit-synchronous Network on Chip with composable and predictable services. - Andreas Hansson 001; Mahesh Subburaman; Kees Goossens (DATE, 2009)

Composable Resource Sharing Based on Latency-Rate Servers. - Benny Akesson; Andreas Hansson 001; Kees Goossens (DSD, 2009)

Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis. - Andreas Hansson 001; Maarten Wiggers; Arno Moonen; Kees Goossens; Marco Bekooij (IET Comput. Digit. Tech., 2009)

Multi-processor programming in the embedded system curriculum. - Andreas Hansson 001; Benny Akesson; Jef L. van Meerbergen (SIGBED Rev., 2009)

CoMPSoC: A template for composable and predictable multi-processor system on chips. - Andreas Hansson 001; Kees Goossens; Marco Bekooij; Jos Huisken (ACM Trans. Design Autom. Electr. Syst., 2009)

The aethereal network on chip after ten years: goals, evolution, lessons, and future. - Kees Goossens; Andreas Hansson 001 (DAC, 2010)

Conservative application-level performance analysis through simulation of MPSoCs. - Andrew Nelson 001; Andreas Hansson 001; Henk Corporaal; Kees Goossens (ESTIMedia, 2010)

Composability and Predictability for Independent Application Development, Verification, and Execution. - Benny Akesson; Anca Mariana Molnos; Andreas Hansson 001; Jude Angelo Ambrose; Kees Goossens (Multiprocessor System-on-Chip, 2011)

A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications. - Andreas Hansson 001; Kees Goossens (Des. Autom. Embed. Syst., 2011)

Design and implementation of an operating system for composable processor sharing. - Andreas Hansson 001; Marcus Ekerhult; Anca Mariana Molnos; Aleksandar Milutinovic; Andrew Nelson 001; Jude Angelo Ambrose; Kees Goossens (Microprocess. Microsystems, 2011)

Introducing DVFS-Management in a Full-System Simulator. - Vasileios Spiliopoulos 001; Akash Bagdia; Andreas Hansson 001; Peter Aldworth; Stefanos Kaxiras (MASCOTS, 2013)

Applying of Quality of Experience to system optimisation. - Sascha Bischoff; Andreas Hansson 001; Bashir M. Al-Hashimi (PATMOS, 2013)

Simulating DRAM controllers for future system architecture exploration. - Andreas Hansson 001; Neha Agarwal; Aasheesh Kolli; Thomas F. Wenisch; Aniruddha N. Udipi (ISPASS, 2014)

Hardware-software interaction for run-time power optimization: A case study of embedded Linux on multicore smartphones. - Anup Das 001; Matthew J. Walker; Andreas Hansson 001; Bashir M. Al-Hashimi; Geoff V. Merrett (ISLPED, 2015)

A full-system approach to analyze the impact of next-generation mobile flash storage. - René de Jong; Andreas Hansson 001 (ISPASS, 2015)

Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs. - Christian Weis; Matthias Jung 001; Omar Naji; Norbert Wehn; Cristiano Santos; Pascal Vivet; Andreas Hansson 001 (ISVLSI, 2015)

A high-level DRAM timing, power and area exploration tool. - Omar Naji; Christian Weis; Matthias Jung 001; Norbert Wehn; Andreas Hansson 001 (SAMOS, 2015)

Elastic traces for fast and accurate system performance exploration. - Radhika Jagtap; Stephan Diestelhorst; Andreas Hansson 001 (ISPASS, 2016)

Thermally-aware composite run-time CPU power models. - Matthew J. Walker; Stephan Diestelhorst; Andreas Hansson 001; Domenico Balsamo; Geoff V. Merrett; Bashir M. Al-Hashimi (PATMOS, 2016)

Exploring system performance using elastic traces: Fast, accurate and portable. - Radhika Jagtap; Stephan Diestelhorst; Andreas Hansson 001; Matthias Jung 001; Norbert Wehn (SAMOS, 2016)

Integrating DRAM power-down modes in gem5 and quantifying their impact. - Radhika Jagtap; Matthias Jung 001; Wendy Elsasser; Christian Weis; Andreas Hansson 001; Norbert Wehn (MEMSYS, 2017)

DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool. - Christian Weis; Abdul Mutaal; Omar Naji; Matthias Jung 001; Andreas Hansson 001; Norbert Wehn (Int. J. Parallel Program., 2017)

Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs. - Matthew J. Walker; Stephan Diestelhorst; Andreas Hansson 001; Anup Das 001; Sheng Yang 003; Bashir M. Al-Hashimi; Geoff V. Merrett (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

The gem5 Simulator: Version 20.0+. - Jason Lowe-Power; Abdul Mutaal Ahmad; Ayaz Akram; Mohammad Alian; Rico Amslinger; Matteo Andreozzi; Adrià Armejach; Nils Asmussen; Srikant Bharadwaj; Gabe Black; Gedare Bloom; Bobby R. Bruce; et al. (CoRR, 2020)