Andreas Hansson

Affiliations:
  • Axelera AI, Eindhoven, The Netherlands
  • ARM Ltd., Cambridge, UK (former)
  • University of Twente, Enschede, The Netherlands (former)
  • Eindhoven University of Technology, The Netherlands (PhD 2009)
  • Lund University, Sweden (former)


According to our database1, Andreas Hansson authored at least 34 papers between 2005 and 2020.

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Bibliography

2020
The gem5 Simulator: Version 20.0+.
CoRR, 2020

2017
Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool.
Int. J. Parallel Program., 2017

Integrating DRAM power-down modes in gem5 and quantifying their impact.
Proceedings of the International Symposium on Memory Systems, 2017

2016
Exploring system performance using elastic traces: Fast, accurate and portable.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Thermally-aware composite run-time CPU power models.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Elastic traces for fast and accurate system performance exploration.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

2015
A high-level DRAM timing, power and area exploration tool.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A full-system approach to analyze the impact of next-generation mobile flash storage.
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

Hardware-software interaction for run-time power optimization: A case study of embedded Linux on multicore smartphones.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2014
Simulating DRAM controllers for future system architecture exploration.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

2013
Applying of Quality of Experience to system optimisation.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Introducing DVFS-Management in a Full-System Simulator.
Proceedings of the 2013 IEEE 21st International Symposium on Modelling, 2013

2011
Design and implementation of an operating system for composable processor sharing.
Microprocess. Microsystems, 2011

A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications.
Des. Autom. Embed. Syst., 2011

Composability and Predictability for Independent Application Development, Verification, and Execution.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2010
Conservative application-level performance analysis through simulation of MPSoCs.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

The aethereal network on chip after ten years: goals, evolution, lessons, and future.
Proceedings of the 47th Design Automation Conference, 2010

2009
CoMPSoC: A template for composable and predictable multi-processor system on chips.
ACM Trans. Design Autom. Electr. Syst., 2009

Multi-processor programming in the embedded system curriculum.
SIGBED Rev., 2009

Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis.
IET Comput. Digit. Tech., 2009

Composable Resource Sharing Based on Latency-Rate Servers.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Aelite: A flit-synchronous Network on Chip with composable and predictable services.
Proceedings of the Design, Automation and Test in Europe, 2009

An on-chip interconnect and protocol stack for multiple communication paradigms and programming models.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
A monitoring-aware network-on-chip design flow.
J. Syst. Archit., 2008

Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

2007
A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic.
VLSI Design, 2007

Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip.
VLSI Design, 2007

Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2005
A unified approach to constrained mapping and routing on network-on-chip architectures.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005


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