Andreas Koch

According to our database1, Andreas Koch authored at least 95 papers between 1997 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2019
Active Storage.
Proceedings of the Encyclopedia of Big Data Technologies., 2019

Hardware-Assisted Transaction Processing: NVM.
Proceedings of the Encyclopedia of Big Data Technologies., 2019

Exact and Practical Modulo Scheduling for High-Level Synthesis.
TRETS, 2019

Native Storage Techniques for Data Management.
Proceedings of the 35th IEEE International Conference on Data Engineering, 2019

Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling.
Proceedings of the Euro-Par 2019: Parallel Processing, 2019

IPA-IDX: In-Place Appends for B-Tree Indices.
Proceedings of the 15th International Workshop on Data Management on New Hardware, 2019

Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2019

UltraSynth: Integration of a CGRA into a Control Engineering Environment.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

nativeNDP: Processing Big Data Analytics on Native Storage Nodes.
Proceedings of the Advances in Databases and Information Systems, 2019

2018
Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

ILP-Based Modulo Scheduling and Binding for Register Minimization.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-Level Synthesis.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

NoFTL-KV: TacklingWrite-Amplification on KV-Stores with Native Storage Management.
Proceedings of the 21th International Conference on Extending Database Technology, 2018

GeMS: a generator for modulo scheduling problems: work in progress.
Proceedings of the International Conference on Compilers, 2018

Improved High-Level Synthesis for Complex CellML Models.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
Synthesis of interleaved multithreaded accelerators from OpenMP loops.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Energy-efficient reconfiguration of flash-based FPGAs in heterogeneous wireless sensor nodes.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

A Performance and Energy Evaluation of OpenCL-accelerated Molecular Docking.
Proceedings of the 5th International Workshop on OpenCL, 2017

OpenMP device offloading to FPGA accelerators.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016
Heterogeneous Wireless Sensor Nodes that Target the Internet of Things.
IEEE Micro, 2016

Detecting Kernels Suitable for C-Based High-Level Hardware Synthesis.
Proceedings of the 2016 Intl IEEE Conferences on Ubiquitous Intelligence & Computing, 2016

A scalable latency-insensitive architecture for FPGA-accelerated semi-global matching in stereo vision applications.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

High-level synthesis of resource-shared microarchitectures from irregular complex C-code.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

A Scalable High-Performance Hardware Architecture for Real-Time Stereo Vision by Semi-Global Matching.
Proceedings of the 2016 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2016

ILP-based modulo scheduling for high-level synthesis.
Proceedings of the 2016 International Conference on Compilers, 2016

2015
ffLink: A Lightweight High-Performance Open-Source PCI Express Gen3 Interface for Reconfigurable Accelerators.
SIGARCH Computer Architecture News, 2015

A heterogeneous system architecture for low-power wireless sensor nodes in compute-intensive distributed applications.
Proceedings of the 40th IEEE Local Computer Networks Conference Workshops, 2015

Accelerated clock drift estimation for high-precision wireless time-synchronization.
Proceedings of the 40th IEEE Local Computer Networks Conference Workshops, 2015

Optimized high-level synthesis of SMT multi-threaded hardware accelerators.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Domain-specific optimisation for the high-level synthesis of CellML-based simulation accelerators.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014
A Reconfigurable Platform and Programming Tools for High-Level Network Applications Demonstrated as a Hardware Honeypot.
IEEE Journal on Selected Areas in Communications, 2014

An energy-efficient wireless routing protocol for distributed structural health monitoring.
Proceedings of the 7th IFIP Wireless and Mobile Networking Conference, 2014

Low-latency double-precision floating-point division for FPGAs.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Integrating FPGA-based processing elements into a runtime for parallel heterogeneous computing.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Automatic high-level synthesis of multi-threaded hardware accelerators.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

PHAT: A technology for prototyping parallel heterogeneous architectures.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Synthilation: JIT-compilation of microinstruction sequences in AMIDAR processors.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Hardware-Accelerated Data Compression in Low-Power Wireless Sensor Networks.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
Hardware/software co-compilation with the Nymble system.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

FPGA-accelerated color edge detection using a Geometric-Algebra-to-Verilog compiler.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Architecture Exploration of High-Performance Floating-Point Fused Multiply-Add Units and their Automatic Use in High-Level Synthesis.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

2012
Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers.
TRETS, 2012

NetStage/DPR: A self-reconfiguring platform for active and passive network security operations.
Microprocessors and Microsystems - Embedded Hardware Design, 2012

Preface - ARC.
Microprocessors and Microsystems - Embedded Hardware Design, 2012

A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection.
Int. J. Reconfig. Comp., 2012

HaLOEWEn: A heterogeneous reconfigurable sensor node for distributed structural health monitoring.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Energy-efficient heterogeneous reconfigurable sensor node for distributed structural health monitoring.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Malacoda: towards high-level compilation of network security applications on reconfigurable hardware.
Proceedings of the Symposium on Architecture for Networking and Communications Systems, 2012

2011
A novel network platform for secure and efficient malware collection based on reconfigurable hardware logic.
Proceedings of the 2011 World Congress on Internet Security, 2011

Evaluation of speculative execution techniques for high-level language to hardware compilation.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

RAP: More Efficient Memory Access in Highly Speculative Execution on Reconfigurable Adaptive Computers.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Precore - A Token-Based Speculation Architecture for High-Level Language to Hardware Compilation.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

A Scalable Multi-FPGA Platform for Complex Networking Applications.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

MARC II: A parametrized speculative multi-ported memory subsystem for reconfigurable computers.
Proceedings of the Design, Automation and Test in Europe, 2011

NetStage/DPR: A Self-adaptable FPGA Platform for Application-Level Network Security.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization.
IEEE Trans. Computers, 2010

Accelerating high-level engineering computations by automatic compilation of Geometric Algebra to hardware accelerators.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

A Dynamically Reconfigured Network Platform for High-Speed Malware Collection.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

An FPGA-based scalable platform for high-speed malware collection in large IP networks.
Proceedings of the International Conference on Field-Programmable Technology, 2010

MalCoBox: Designing a 10 Gb/s Malware Collection Honeypot Using Reconfigurable Technology.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

A Flexible Compute and Memory Infrastructure for High-Level Language to Hardware Compilation.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Side-Channel Resistance Evaluation of a Neural Network Based Lightweight Cryptography Scheme.
Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010

Compiling Geometric Algebra Computations into Reconfigurable Hardware Accelerators.
Proceedings of the Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010

Adaptive Computing Systems and Their Design Tools.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

Gaalop - High Performance Parallel Computing Based on Conformal Geometric Algebra.
Proceedings of the Geometric Algebra Computing - in Engineering and Computer Science., 2010

2009
A Fast GPU Implementation for Solving Sparse Ill-Posed Linear Equation Systems.
Proceedings of the Parallel Processing and Applied Mathematics, 2009

Challenges of Electronic CAD in the Nano Scale Era.
Proceedings of the Informatik 2009: Im Focus das Leben, 2009

Acceleration and Energy Efficiency of a Geometric Algebra Computation using Reconfigurable Computers and GPUs.
Proceedings of the FCCM 2009, 2009

2008
Rekonfigurierbare Architekturen.
Informatik Spektrum, 2008

Inverse kinematics of a humanoid robot based on conformal geometric algebra using optimized code generation.
Proceedings of the 8th IEEE-RAS International Conference on Humanoid Robots, 2008

Efficient Inverse Kinematics Algorithm Based on Conformal Geometric Algebra - Using Reconfigurable Hardware.
Proceedings of the GRAPP 2008, 2008

Low-latency high-bandwidth HW/SW communication in a virtual memory environment.
Proceedings of the FPL 2008, 2008

Memory access parallelisation in high-level language compilation for reconfigurable adaptive computers.
Proceedings of the FPL 2008, 2008

Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Editorial - Field-programmable logic and applications.
IET Computers & Digital Techniques, 2007

An Execution Model for Hardware/Software Compilation and its System-Level Realization.
Proceedings of the FPL 2007, 2007

Comrade - A Compiler for Adaptive Computing Systems Using a Novel Fast Speculation Technique.
Proceedings of the FPL 2007, 2007

2006
Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
High-Level-Language Compilation for Reconfigurable Computers.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Configuration Merging for Adaptive Computer Applications.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
HW/SW Co-design by Automatic Embedding of Complex IP Cores.
Proceedings of the Field Programmable Logic and Application, 2004

Wavelet-Based Image Compression on the Reconfigurable Computer ACE-V.
Proceedings of the Field Programmable Logic and Application, 2004

Architecture-Independent Meta-optimization by Aggressive Tail Splitting.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

Verbesserte Hardware-Software-Partitionierung für Adaptive Computer.
Proceedings of the ARCS 2004, 2004

2003
Fast Region Labeling on the Reconfigurable Platform ACE-V.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

An Improved Intermediate Representation for Datapath Generation.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

2002
Module Generators Driving the Compilation for Adaptive Computing Systems.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2000
Memory Access Schemes for Configurable Processors.
Proceedings of the Field-Programmable Logic and Applications, 2000

1999
A Processor for Artificial Life Simulation.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

Enabling Automatic Module Generation for FCCM Compilers.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1997
Regular datapaths on field programmable gate arrays.
PhD thesis, 1997


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