Regular datapaths on field programmable gate arrays. - Andreas Koch 001 (1997)

Enabling Automatic Module Generation for FCCM Compilers. - Andreas Koch 001 (FCCM, 1999)

A Processor for Artificial Life Simulation. - Matthias Böge; Andreas Koch 001 (FPL, 1999)

Memory Access Schemes for Configurable Processors. - Holger Lange; Andreas Koch 001 (FPL, 2000)

Module Generators Driving the Compilation for Adaptive Computing Systems. - Andreas Koch 001; Nico Kasprzyk (FCCM, 2002)

An Improved Intermediate Representation for Datapath Generation. - Nico Kasprzyk; Andreas Koch 001; Ulrich Golze; Michael Rock (Engineering of Reconfigurable Systems and Algorithms, 2003)

Fast Region Labeling on the Reconfigurable Platform ACE-V. - Christian Schmidt 014; Andreas Koch 001 (FPL, 2003)

Verbesserte Hardware-Software-Partitionierung für Adaptive Computer. - Nico Kasprzyk; Andreas Koch 001 (ARCS Workshops, 2004)

Architecture-Independent Meta-optimization by Aggressive Tail Splitting. - Michael Rock; Andreas Koch 001 (Euro-Par, 2004)

Wavelet-Based Image Compression on the Reconfigurable Computer ACE-V. - Hagen Gädke; Andreas Koch 001 (FPL, 2004)

HW/SW Co-design by Automatic Embedding of Complex IP Cores. - Holger Lange; Andreas Koch 001 (FPL, 2004)

Configuration Merging for Adaptive Computer Applications. - Nico Kasprzyk; Jan van der Veen; Andreas Koch 001 (FPL, 2005)

High-Level-Language Compilation for Reconfigurable Computers. - Andreas Koch 001; Nico Kasprzyk (ReCoSoC, 2005)

Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays. - Florian Stock; Andreas Koch 001 (FPL, 2006)

Comrade - A Compiler for Adaptive Computing Systems Using a Novel Fast Speculation Technique. - Hagen Gädke; Andreas Koch 001 (FPL, 2007)

An Execution Model for Hardware/Software Compilation and its System-Level Realization. - Holger Lange; Andreas Koch 001 (FPL, 2007)

Editorial - Field-programmable logic and applications. - Philip Heng Wai Leong; Andreas Koch 001; Eduardo I. Boemo (IET Comput. Digit. Tech., 2007)

Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens. - Hagen Gädke; Andreas Koch 001 (ARC, 2008)

Memory access parallelisation in high-level language compilation for reconfigurable adaptive computers. - Hagen Gädke; Florian Stock; Andreas Koch 001 (FPL, 2008)

Low-latency high-bandwidth HW/SW communication in a virtual memory environment. - Holger Lange; Andreas Koch 001 (FPL, 2008)

Efficient Inverse Kinematics Algorithm Based on Conformal Geometric Algebra - Using Reconfigurable Hardware. - Dietmar Hildenbrand; Holger Lange; Florian Stock; Andreas Koch 001 (GRAPP, 2008)

Inverse kinematics of a humanoid robot based on conformal geometric algebra using optimized code generation. - Joachim Pitt; Dietmar Hildenbrand; Maximilian Stelzer; Andreas Koch 001 (Humanoids, 2008)

Rekonfigurierbare Architekturen. - Mladen Berekovic; Christian Hochberger; Andreas Koch 001 (Inform. Spektrum, 2008)

Acceleration and Energy Efficiency of a Geometric Algebra Computation using Reconfigurable Computers and GPUs. - Holger Lange; Florian Stock; Andreas Koch 001; Dietmar Hildenbrand (FCCM, 2009)

Challenges of Electronic CAD in the Nano Scale Era. - Christian Hochberger; Andreas Koch 001 (GI Jahrestagung, 2009)

A Fast GPU Implementation for Solving Sparse Ill-Posed Linear Equation Systems. - Florian Stock; Andreas Koch 001 (PPAM (1), 2009)

Gaalop - High Performance Parallel Computing Based on Conformal Geometric Algebra. - Dietmar Hildenbrand; Joachim Pitt; Andreas Koch 001 (Geometric Algebra Computing, 2010)

Adaptive Computing Systems and Their Design Tools. - Andreas Koch 001 (Dynamically Reconfigurable Systems, 2010)

Compiling Geometric Algebra Computations into Reconfigurable Hardware Accelerators. - Jens Huthmann; Peter Müller 010; Florian Stock; Dietmar Hildenbrand; Andreas Koch 001 (Dynamically Reconfigurable Architectures, 2010)

Side-Channel Resistance Evaluation of a Neural Network Based Lightweight Cryptography Scheme. - Marc Stöttinger; Sorin A. Huss; Sascha Mühlbach; Andreas Koch 001 (EUC, 2010)

A Flexible Compute and Memory Infrastructure for High-Level Language to Hardware Compilation. - Hagen Gädke-Lütjens; Benjamin Thielmann; Andreas Koch 001 (FPL, 2010)

A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor. - Gerald Hempel; Christian Hochberger; Andreas Koch 001 (FPL, 2010)

MalCoBox: Designing a 10 Gb/s Malware Collection Honeypot Using Reconfigurable Technology. - Sascha Mühlbach; Martin Brunner; Christopher Roblee; Andreas Koch 001 (FPL, 2010)

An FPGA-based scalable platform for high-speed malware collection in large IP networks. - Sascha Mühlbach; Andreas Koch 001 (FPT, 2010)

A Dynamically Reconfigured Network Platform for High-Speed Malware Collection. - Sascha Mühlbach; Andreas Koch 001 (ReConFig, 2010)

Accelerating high-level engineering computations by automatic compilation of Geometric Algebra to hardware accelerators. - Jens Huthmann; Peter Müller 010; Florian Stock; Dietmar Hildenbrand; Andreas Koch 001 (ICSAMOS, 2010)

Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization. - Holger Lange; Andreas Koch 001 (IEEE Trans. Computers, 2010)

Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications. - Andreas Engel 003; Björn Liebig; Andreas Koch 001 (ARC, 2011)

NetStage/DPR: A Self-adaptable FPGA Platform for Application-Level Network Security. - Sascha Mühlbach; Andreas Koch 001 (ARC, 2011)

MARC II: A parametrized speculative multi-ported memory subsystem for reconfigurable computers. - Holger Lange; Thorsten Wink; Andreas Koch 001 (DATE, 2011)

A Scalable Multi-FPGA Platform for Complex Networking Applications. - Sascha Mühlbach; Andreas Koch 001 (FCCM, 2011)

Precore - A Token-Based Speculation Architecture for High-Level Language to Hardware Compilation. - Benjamin Thielmann; Jens Huthmann; Andreas Koch 001 (FPL, 2011)

RAP: More Efficient Memory Access in Highly Speculative Execution on Reconfigurable Adaptive Computers. - Benjamin Thielmann; Thorsten Wink; Jens Huthmann; Andreas Koch 001 (ReConFig, 2011)

Evaluation of speculative execution techniques for high-level language to hardware compilation. - Benjamin Thielmann; Jens Huthmann; Andreas Koch 001 (ReCoSoC, 2011)

A novel network platform for secure and efficient malware collection based on reconfigurable hardware logic. - Sascha Mühlbach; Andreas Koch 001 (WorldCIS, 2011)

Malacoda: towards high-level compilation of network security applications on reconfigurable hardware. - Sascha Mühlbach; Andreas Koch 001 (ANCS, 2012)

Energy-efficient heterogeneous reconfigurable sensor node for distributed structural health monitoring. - Andreas Engel 003; Björn Liebig; Andreas Koch 001 (DASIP, 2012)

HaLOEWEn: A heterogeneous reconfigurable sensor node for distributed structural health monitoring. - Andreas Engel 003; Björn Liebig; Andreas Koch 001 (DASIP, 2012)

A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection. - Sascha Mühlbach; Andreas Koch 001 (Int. J. Reconfigurable Comput., 2012)

Preface - ARC. - Andreas Koch 001; Roger F. Woods (Microprocess. Microsystems, 2012)

NetStage/DPR: A self-reconfiguring platform for active and passive network security operations. - Sascha Mühlbach; Andreas Koch 001 (Microprocess. Microsystems, 2012)

Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers. - Benjamin Thielmann; Jens Huthmann; Andreas Koch 001 (ACM Trans. Reconfigurable Technol. Syst., 2012)

Architecture Exploration of High-Performance Floating-Point Fused Multiply-Add Units and their Automatic Use in High-Level Synthesis. - Björn Liebig; Jens Huthmann; Andreas Koch 001 (IPDPS Workshops, 2013)

FPGA-accelerated color edge detection using a Geometric-Algebra-to-Verilog compiler. - Florian Stock; Andreas Koch 001; Dietmar Hildenbrand (ISSoC, 2013)

Hardware/software co-compilation with the Nymble system. - Jens Huthmann; Björn Liebig; Julian Oppermann; Andreas Koch 001 (ReCoSoC, 2013)

Hardware-Accelerated Data Compression in Low-Power Wireless Sensor Networks. - Andreas Engel 003; Andreas Koch 001 (ARC, 2014)

Synthilation: JIT-compilation of microinstruction sequences in AMIDAR processors. - Christian Hochberger; Lukas Johannes Jung; Andreas Engel 003; Andreas Koch 001 (DASIP, 2014)

PHAT: A technology for prototyping parallel heterogeneous architectures. - Thorsten Wink; Andreas Koch 001 (DASIP, 2014)

Automatic high-level synthesis of multi-threaded hardware accelerators. - Jens Huthmann; Julian Oppermann; Andreas Koch 001 (FPL, 2014)

Integrating FPGA-based processing elements into a runtime for parallel heterogeneous computing. - David de la Chevallerie; Jens Korinth; Andreas Koch 001 (FPT, 2014)

Low-latency double-precision floating-point division for FPGAs. - Björn Liebig; Andreas Koch 001 (FPT, 2014)

An energy-efficient wireless routing protocol for distributed structural health monitoring. - Andreas Engel 003; Andreas Koch 001 (WMNC, 2014)

A Reconfigurable Platform and Programming Tools for High-Level Network Applications Demonstrated as a Hardware Honeypot. - Sascha Mühlbach; Andreas Koch 001 (IEEE J. Sel. Areas Commun., 2014)

An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures. - Jens Korinth; David de la Chevallerie; Andreas Koch 001 (FCCM, 2015)

Domain-specific optimisation for the high-level synthesis of CellML-based simulation accelerators. - Julian Oppermann; Andreas Koch 001; Ting Yu 012; Oliver Sinnen (FPL, 2015)

Optimized high-level synthesis of SMT multi-threaded hardware accelerators. - Jens Huthmann; Andreas Koch 001 (FPT, 2015)

Accelerated clock drift estimation for high-precision wireless time-synchronization. - Andreas Engel 003; Andreas Koch 001 (LCN Workshops, 2015)

A heterogeneous system architecture for low-power wireless sensor nodes in compute-intensive distributed applications. - Andreas Engel 003; Andreas Koch 001; Thomas Siebel (LCN Workshops, 2015)

ThreadPoolComposer - An Open-Source FPGA Toolchain for Software Developers. - Jens Korinth; David de la Chevallerie; Andreas Koch 001 (CoRR, 2015)

ffLink: A Lightweight High-Performance Open-Source PCI Express Gen3 Interface for Reconfigurable Accelerators. - David de la Chevallerie; Jens Korinth; Andreas Koch 001 (SIGARCH Comput. Archit. News, 2015)

ILP-based modulo scheduling for high-level synthesis. - Julian Oppermann; Andreas Koch 001; Melanie Reuter-Oppermann; Oliver Sinnen (CASES, 2016)

A Scalable High-Performance Hardware Architecture for Real-Time Stereo Vision by Semi-Global Matching. - Jaco A. Hofmann; Jens Korinth; Andreas Koch 001 (CVPR Workshops, 2016)

High-level synthesis of resource-shared microarchitectures from irregular complex C-code. - Björn Liebig; Andreas Koch 001 (FPT, 2016)

A scalable latency-insensitive architecture for FPGA-accelerated semi-global matching in stereo vision applications. - Jaco A. Hofmann; Jens Korinth; Andreas Koch 001 (ReConFig, 2016)

Detecting Kernels Suitable for C-Based High-Level Hardware Synthesis. - Julian Oppermann; Andreas Koch 001 (UIC/ATC/ScalCom/CBDCom/IoP/SmartWorld, 2016)

Heterogeneous Wireless Sensor Nodes that Target the Internet of Things. - Andreas Engel 003; Andreas Koch 001 (IEEE Micro, 2016)

OpenMP device offloading to FPGA accelerators. - Lukas Sommer; Jens Korinth; Andreas Koch 001 (ASAP, 2017)

A Performance and Energy Evaluation of OpenCL-accelerated Molecular Docking. - Leonardo Solis-Vasquez; Andreas Koch 001 (IWOCL, 2017)

Energy-efficient reconfiguration of flash-based FPGAs in heterogeneous wireless sensor nodes. - Andreas Engel 003; Andreas Koch 001 (ReConFig, 2017)

Synthesis of interleaved multithreaded accelerators from OpenMP loops. - Lukas Sommer; Julian Oppermann; Jaco A. Hofmann; Andreas Koch 001 (ReConFig, 2017)

Improved High-Level Synthesis for Complex CellML Models. - Björn Liebig; Julian Oppermann; Oliver Sinnen; Andreas Koch 001 (ARC, 2018)

GeMS: a generator for modulo scheduling problems: work in progress. - Julian Oppermann; Sebastian Vollbrecht; Melanie Reuter-Oppermann; Oliver Sinnen; Andreas Koch 001 (CASES, 2018)

NoFTL-KV: TacklingWrite-Amplification on KV-Stores with Native Storage Management. - Tobias Vinçon; Sergej Hardock; Christian Riegger; Julian Oppermann; Andreas Koch 001; Ilia Petrov 001 (EDBT, 2018)

Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-Level Synthesis. - Julian Oppermann; Melanie Reuter-Oppermann; Lukas Sommer; Oliver Sinnen; Andreas Koch 001 (FPL, 2018)

ILP-Based Modulo Scheduling and Binding for Register Minimization. - Patrick Sittel; Martin Kumm; Julian Oppermann; Konrad Möller; Peter Zipf; Andreas Koch 001 (FPL, 2018)

Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators. - Lukas Sommer; Julian Oppermann; Alejandro Molina 001; Carsten Binnig; Kristian Kersting; Andreas Koch 001 (ICCD, 2018)

nativeNDP: Processing Big Data Analytics on Native Storage Nodes. - Tobias Vinçon; Sergey Hardock; Christian Riegger; Andreas Koch 001; Ilia Petrov 001 (ADBIS, 2019)

High-Performance In-Network Data Processing. - Jaco A. Hofmann; Lasse Thostrup; Tobias Ziegler 001; Carsten Binnig; Andreas Koch 001 (ADMS@VLDB, 2019)

The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems. - Jens Korinth; Jaco A. Hofmann; Carsten Heinz; Andreas Koch 001 (ARC, 2019)

UltraSynth: Integration of a CGRA into a Control Engineering Environment. - Dennis Wolf 001; Tajas Ruschke; Christian Hochberger; Andreas Engel 003; Andreas Koch 001 (ARC, 2019)

Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language. - Robin Kruppe; Julian Oppermann; Lukas Sommer; Andreas Koch 001 (CGO, 2019)

Online Reprogrammable Multi Tenant Switches. - Johannes Krude; Jaco A. Hofmann; Matthias Eichholz 001; Klaus Wehrle; Andreas Koch 001; Mira Mezini (ENCP@CoNEXT, 2019)

IPA-IDX: In-Place Appends for B-Tree Indices. - Sergey Hardock; Andreas Koch 001; Tobias Vinçon; Ilia Petrov 001 (DaMoN, 2019)

DAPHNE - An automotive benchmark suite for parallel programming models on embedded heterogeneous platforms: work-in-progress. - Lukas Sommer; Florian Stock; Leonardo Solis-Vasquez; Andreas Koch 001 (EMSOFT Companion, 2019)

Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling. - Julian Oppermann; Patrick Sittel; Martin Kumm; Melanie Reuter-Oppermann; Andreas Koch 001; Oliver Sinnen (Euro-Par, 2019)

Native Storage Techniques for Data Management. - Ilia Petrov 001; Andreas Koch 001; Sergey Hardock; Tobias Vinçon; Christian Riegger (ICDE, 2019)

SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis. - Julian Oppermann; Lukas Sommer; Lukas Weber; Melanie Reuter-Oppermann; Andreas Koch 001; Oliver Sinnen (FPT, 2019)

Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs. - Lukas Weber; Lukas Sommer; Julian Oppermann; Alejandro Molina 001; Kristian Kersting; Andreas Koch 001 (FPT, 2019)

A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors. - Carsten Heinz; Yannick Lavan; Jaco A. Hofmann; Andreas Koch 001 (ReConFig, 2019)

High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud. - Micha Ober; Jaco A. Hofmann; Lukas Sommer; Lukas Weber; Andreas Koch 001 (H2RC@SC, 2019)

Moving Processing to Data: On the Influence of Processing in Memory on Data Management. - Tobias Vinçon; Andreas Koch 001; Ilia Petrov 001 (CoRR, 2019)

Comparison of affinity ranking using AutoDock-GPU and MM-GBSA scores for BACE-1 inhibitors in the D3R Grand Challenge 4. - Lea El-Khoury; Diogo Santos-Martins; Sukanya Sasmal; Jérôme Eberhardt; Giulia Bianco; Francesca Alessandra Ambrosio; Leonardo Solis-Vasquez; Andreas Koch 001; Stefano Forli; David L. Mobley (J. Comput. Aided Mol. Des., 2019)

D3R Grand Challenge 4: prospective pose prediction of BACE1 ligands with AutoDock-GPU. - Diogo Santos-Martins; Jérôme Eberhardt; Giulia Bianco; Leonardo Solis-Vasquez; Francesca Alessandra Ambrosio; Andreas Koch 001; Stefano Forli (J. Comput. Aided Mol. Des., 2019)

SpExSim: assessing kernel suitability for C-based high-level hardware synthesis. - Julian Oppermann; Lukas Sommer; Andreas Koch 001 (J. Supercomput., 2019)

Exact and Practical Modulo Scheduling for High-Level Synthesis. - Julian Oppermann; Melanie Reuter-Oppermann; Lukas Sommer; Andreas Koch 001; Oliver Sinnen (ACM Trans. Reconfigurable Technol. Syst., 2019)

Hardware-Assisted Transaction Processing: NVM. - Ilia Petrov 001; Andreas Koch 001; Tobias Vinçon; Sergey Hardock; Christian Riegger (Encyclopedia of Big Data Technologies, 2019)

Active Storage. - Ilia Petrov 001; Tobias Vinçon; Andreas Koch 001; Julian Oppermann; Sergey Hardock; Christian Riegger (Encyclopedia of Big Data Technologies, 2019)

GPU-Accelerated Drug Discovery with Docking on the Summit Supercomputer: Porting, Optimization, and Application to COVID-19 Research. - Scott LeGrand; Aaron Scheinberg; Andreas F. Tillack; Mathialakan Thavappiragasam; Josh Vincent Vermaas; Rupesh Agarwal; Jeff Larkin; Duncan Poole; Diogo Santos-Martins; Leonardo Solis-Vasquez; Andreas Koch 001; Stefano Forli; et al. (BCB, 2020)

Extending High-Level Synthesis with High-Performance Computing Performance Visualization. - Jens Huthmann; Artur Podobas; Lukas Sommer; Andreas Koch 001; Kentaro Sano (CLUSTER, 2020)

nKV: near-data processing with KV-stores on native computational storage. - Tobias Vinçon; Arthur Bernhardt; Ilia Petrov 001; Lukas Weber; Andreas Koch 001 (DaMoN, 2020)

OpenMP Device Offloading for Embedded Heterogeneous Platforms - Work-in-Progress. - Lukas Sommer; Andreas Koch 001 (EMSOFT, 2020)

Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs. - Lukas Sommer; Lukas Weber; Martin Kumm; Andreas Koch 001 (FCCM, 2020)

On the Necessity of Explicit Cross-Layer Data Formats in Near-Data Processing Systems. - Tobias Vinçon; Arthur Bernhardt; Lukas Weber; Andreas Koch 001; Ilia Petrov 001 (ICDE Workshops, 2020)

OpenMP Device Offloading to FPGAs Using the Nymble Infrastructure. - Jens Huthmann; Lukas Sommer; Artur Podobas; Andreas Koch 001; Kentaro Sano (IWOMP, 2020)

Evaluating the Energy Efficiency of OpenCL-accelerated AutoDock Molecular Docking. - Leonardo Solis-Vasquez; Diogo Santos-Martins; Andreas Koch 001; Stefano Forli (PDP, 2020)

Using Parallel Programming Models for Automotive Workloads on Heterogeneous Systems - a Case Study. - Lukas Sommer; Florian Stock; Leonardo Solis-Vasquez; Andreas Koch 001 (PDP, 2020)

Improving Job Launch Rates in the TaPaSCo FPGA Middleware by Hardware/Software-Co-Design. - Carsten Heinz; Jaco A. Hofmann; Lukas Sommer; Andreas Koch 001 (ROSS@SC, 2020)

Parallelizing Irregular Computations for Molecular Docking. - Leonardo Solis-Vasquez; Diogo Santos-Martins; Andreas F. Tillack; Andreas Koch 001; Jérôme Eberhardt; Stefano Forli (IA3@SC, 2020)

nKV in Action: Accelerating KV-Stores on NativeComputational Storage with Near-Data Processing. - Tobias Vinçon; Lukas Weber; Arthur Bernhardt; Andreas Koch 001; Ilia Petrov 001; Christian Knödler; Sergey Hardock; Sajjad Tamimi; Christian Riegger (Proc. VLDB Endow., 2020)

Supporting On-Chip Dynamic Parallelism for Task-Based Hardware Accelerators. - Carsten Heinz; Andreas Koch 001 (ARC, 2021)

Exploiting 3D Memory for Accelerated In-Network Processing of Hash Joins in Distributed Databases. - Johannes Wirth 002; Jaco A. Hofmann; Lasse Thostrup; Andreas Koch 001; Carsten Binnig (ARC, 2021)

SPNC: Accelerating Sum-Product Network Inference on CPUs and GPUs. - Lukas Sommer; Michael Halkenhäuser; Cristian Axenie; Andreas Koch 001 (ASAP, 2021)

A cost model for NDP-aware query optimization for KV-stores. - Christian Knödler; Tobias Vinçon; Arthur Bernhardt; Ilia Petrov 001; Leonardo Solis-Vasquez; Lukas Weber; Andreas Koch 001 (DaMoN, 2021)

Efficient Physical Page Migrations in Shared Virtual Memory Reconfigurable Computing Systems. - Torben Kalkhof; Andreas Koch 001 (FPT, 2021)

Scalable and Flexible High-Performance In-Network Processing of Hash Joins in Distributed Databases. - Johannes Wirth 002; Jaco A. Hofmann; Lasse Thostrup; Carsten Binnig; Andreas Koch 001 (FPT, 2021)

Optimizing a Hardware Network Stack to Realize an In-Network ML Inference Application. - Marco Hartmann; Lukas Weber; Johannes Wirth 002; Lukas Sommer; Andreas Koch 001 (H2RC@SC, 2021)

Near-Data FPGA-Accelerated Processing of Collective and Inference Operations in Disaggregated Memory Systems. - Carsten Heinz; Andreas Koch 001 (H2RC@SC, 2021)

A Framework for the Automatic Generation of FPGA-based Near-Data Processing Accelerators in Smart Storage Systems. - Lukas Weber; Lukas Sommer; Leonardo Solis-Vasquez; Tobias Vinçon; Christian Knödler; Arthur Bernhardt; Ilia Petrov 001; Andreas Koch 001 (IPDPS Workshops, 2021)

SPNC: Fast Sum-Product Network Inference. - Lukas Sommer; Cristian Axenie; Andreas Koch 001 (PKDD/ECML Workshops (1), 2021)

Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs. - Hanna Kruppe; Lukas Sommer; Lukas Weber; Julian Oppermann; Cristian Axenie; Andreas Koch 001 (SAMOS, 2021)

RT-LIFE: Portable RISC-V Interface for Real-Time Lightweight Security Enforcement. - Christoph Spang 001; Florian Meisel; Andreas Koch 001 (SAMOS, 2021)

Mapping Irregular Computations for Molecular Docking to the SX-Aurora TSUBASA Vector Engine. - Leonardo Solis-Vasquez; Erich Focht; Andreas Koch 001 (IA3@SC, 2021)

Porting and Optimizing Molecular Docking onto the SX-Aurora TSUBASA Vector Computer. - Leonardo Solis-Vasquez; Erich Focht; Andreas Koch 001 (Supercomput. Front. Innov., 2021)

The TaPaSCo Open-Source Toolflow. - Carsten Heinz; Jaco A. Hofmann; Jens Korinth; Lukas Sommer; Lukas Weber; Andreas Koch 001 (J. Signal Process. Syst., 2021)

UltraSynth: Insights of a CGRA Integration into a Control Engineering Environment. - Dennis Wolf 001; Andreas Engel 003; Tajas Ruschke; Andreas Koch 001; Christian Hochberger (J. Signal Process. Syst., 2021)

IPEC: Open-Source Design Automation for Inter-Processing Element Communication. - David Volz; Christoph Spang 001; Andreas Koch 001 (ARC, 2022)

SPNC: An Open-Source MLIR-Based Compiler for Fast Sum-Product Network Inference on CPUs and GPUs. - Lukas Sommer; Cristian Axenie; Andreas Koch 001 (CGO, 2022)

SCAIE-V: an open-source SCAlable interface for ISA extensions for RISC-V processors. - Mihaela Damian; Julian Oppermann; Christoph Spang 001; Andreas Koch 001 (DAC, 2022)

Result-Set Management for NDP Operations on Smart Storage. - Tobias Vinçon; Christian Knödler; Arthur Bernhardt; Leonardo Solis-Vasquez; Lukas Weber; Andreas Koch 001; Ilia Petrov 001 (DaMoN, 2022)

The Scale4Edge RISC-V Ecosystem. - Wolfgang Ecker; Peer Adelt; Wolfgang Müller 003; Reinhold Heckmann; Milos Krstic; Vladimir Herdt; Rolf Drechsler; Gerhard Angst; Ralf Wimmer 001; Andreas Mauderer; Rafael Stahl; Karsten Emrich; et al. (DATE, 2022)

Cache-Coherent Shared Locking for Transactionally Consistent Updates in Near-Data Processing DBMS on Smart Storage. - Arthur Bernhardt; Sajjad Tamimi; Florian Stock; Tobias Vinçon; Andreas Koch 001; Ilia Petrov 001 (EDBT, 2022)

An Evaluation of Using CCIX for Cache-Coherent Host-FPGA Interfacing. - Sajjad Tamimi; Florian Stock; Andreas Koch 001; Arthur Bernhardt; Ilia Petrov 001 (FCCM, 2022)

Direct Device-to-Device Physical Page Migrations in Multi-FPGA Shared Virtual Memory Systems. - Torben Kalkhof; Andreas Koch 001 (FPL, 2022)

DeLiBA: An Open-Source Hardware/Software Framework for the Development of Linux Block I/O Accelerators. - Babar Khan; Carsten Heinz; Andreas Koch 001 (FPL, 2022)

neoDBMS: In-situ Snapshots for Multi-Version DBMS on Native Computational Storage. - Arthur Bernhardt; Sajjad Tamimi; Tobias Vinçon; Christian Knödler; Florian Stock; Carsten Heinz; Andreas Koch 001; Ilia Petrov 001 (ICDE, 2022)

Exploiting High-Bandwidth Memory for FPGA-Acceleration of Inference on Sum-Product Networks. - Lukas Weber; Johannes Wirth 002; Lukas Sommer; Andreas Koch 001 (IPDPS Workshops, 2022)

On the necessity of explicit cross-layer data formats in near-data processing systems. - Lukas Weber; Tobias Vinçon; Christian Knödler; Leonardo Solis-Vasquez; Arthur Bernhardt; Ilia Petrov 001; Andreas Koch 001 (Distributed Parallel Databases, 2022)

Benchmarking the performance of irregular computations in AutoDock-GPU molecular docking. - Leonardo Solis-Vasquez; Andreas F. Tillack; Diogo Santos-Martins; Andreas Koch 001; Scott LeGrand; Stefano Forli (Parallel Comput., 2022)

Near-Data Processing in Database Systems on Native Computational Storage under HTAP Workloads. - Tobias Vinçon; Christian Knödler; Leonardo Solis-Vasquez; Arthur Bernhardt; Sajjad Tamimi; Lukas Weber; Florian Stock; Andreas Koch 001; Ilia Petrov 001 (Proc. VLDB Endow., 2022)

On-Chip and Distributed Dynamic Parallelism for Task-based Hardware Accelerators. - Carsten Heinz; Andreas Koch 001 (J. Signal Process. Syst., 2022)

DExIE - An IoT-Class Hardware Monitor for Real-Time Fine-Grained Control-Flow Integrity. - Christoph Spang 001; Yannick Lavan; Marco Hartmann; Florian Meisel; Andreas Koch 001 (J. Signal Process. Syst., 2022)

NVMulator: A Configurable Open-Source Non-volatile Memory Emulator for FPGAs. - Sajjad Tamimi; Arthur Bernhardt; Florian Stock; Ilia Petrov 001; Andreas Koch 001 (ARC, 2023)

pimDB: From Main-Memory DBMS to Processing-In-Memory DBMS-Engines on Intelligent Memories. - Arthur Bernhardt; Andreas Koch 001; Ilia Petrov 001 (DaMoN, 2023)

TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing. - Florian Meisel; David Volz; Christoph Spang 001; Dat Tran; Andreas Koch 001 (DASIP, 2023)

Experiences Migrating CUDA to SYCL: A Molecular Docking Case Study. - Leonardo Solis-Vasquez; Edward Mascarenhas; Andreas Koch 001 (IWOCL, 2023)

Software-Defined Wireless Communication Systems for Heterogeneous Architectures. - David Volz; Andreas Koch 001; Bastian Bloessl (MobiCom, 2023)

$ mathrm {DD text {-}MPU}$: Dynamic and Distributed Memory Protection Unit for Embedded System-on-Chips. - Carsten Heinz; Andreas Koch 001 (SAMOS, 2023)

Altis-SYCL: Migrating Altis Benchmarking Suite from CUDA to SYCL for GPUs and FPGAs. - Christoph Weckert; Leonardo Solis-Vasquez; Julian Oppermann; Andreas Koch 001; Oliver Sinnen (SC Workshops, 2023)

PQC-HA: A Framework for Prototyping and In-Hardware Evaluation of Post-Quantum Cryptography Hardware Accelerators. - Richard Sattel; Christoph Spang 001; Carsten Heinz; Andreas Koch 001 (CoRR, 2023)

Introduction to the Special Issue on FPT 2021. - Andreas Koch 001; Wei Zhang 012 (ACM Trans. Reconfigurable Technol. Syst., 2023)

Enabling FPGA and AI Engine Tasks in the HPX Programming Framework for Heterogeneous High-Performance Computing. - Torben Kalkhof; Carsten Heinz; Andreas Koch 001 (ARC, 2024)

Graphtoy: Fast Software Simulation of Applications for AMD's AI Engines. - Jonathan Strobl; Leonardo Solis-Vasquez; Yannick Lavan; Andreas Koch 001 (ARC, 2024)

Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language. - Julian Oppermann; Brindusa Mihaela Damian-Kosterhon; Florian Meisel; Tammo Mürmann; Eyck Jentzsch; Andreas Koch 001 (ASPLOS (3), 2024)

A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. - Paul Palomero Bernardo; Patrick Schmid; Oliver Bringmann 001; Mohammed Iftekhar; Babak Sadiye; Wolfgang Mueller; Andreas Koch 001; Eyck Jentzsch; Axel Sauer; Ingo Feldner; Wolfgang Ecker (DATE, 2024)

TaPaS Co-AIE: An Open-Source Framework for Streaming-Based Heterogeneous Acceleration Using AMD AI Engines. - Carsten Heinz; Torben Kalkhof; Yannick Lavan; Andreas Koch 001 (IPDPS (Workshops), 2024)

Speeding-Up LULESH on HPX: Useful Tricks and Lessons Learned using a Many-Task-Based Approach. - Torben Kalkhof; Andreas Koch 001 (SC Workshops, 2024)

DeLiBA-K: Speeding-up Hardware-Accelerated Distributed Storage Access by Tighter Linux Kernel Integration and Use of a Modern API. - Babar Khan; Andreas Koch 001 (SC Workshops, 2024)

COSSEA: Context-based SoC Security Enforcement Architecture. - Carsten Heinz; Andreas Koch 001 (SOCC, 2024)

A survey on FPGA-based accelerator for ML models. - Feng Yan; Andreas Koch 001; Oliver Sinnen (CoRR, 2024)

TaPaFuzz: Hardware-accelerated RISC-V bare-metal firmware fuzzing using rapid job launches. - Florian Meisel; Christoph Spang 001; David Volz; Andreas Koch 001 (J. Syst. Archit., 2024)

Zero-sided RDMA: Network-driven Data Shuffling for Disaggregated Heterogeneous Cloud DBMSs. - Matthias Jasny; Lasse Thostrup; Sajjad Tamimi; Andreas Koch 001; Zsolt István; Carsten Binnig (Proc. ACM Manag. Data, 2024)

The Open-source DeLiBA2 Hardware/Software Framework for Distributed Storage Accelerators. - Babar Khan; Carsten Heinz; Andreas Koch 001 (ACM Trans. Reconfigurable Technol. Syst., 2024)

Introduction to the Special Issue on FPL 2022. - Andreas Koch 001; Kentaro Sano (ACM Trans. Reconfigurable Technol. Syst., 2024)

SCAL: An Open-Source Scalable Core Adaptation Layer for Interfacing RISC-V ISA Extensions. - Brindusa Mihaela Damian-Kosterhon; Florian Meisel; Andreas Koch 001 (ASAP, 2025)

Improving mapping of convolutional neural networks on FPGAs through tailored macro sizes. - Brindusa Mihaela Damian-Kosterhon; Andreas Koch 001; Felix Kosterhon; Lucian Petrica (IPDPS (Workshops), 2025)

DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP. - Sajjad Tamimi; Arthur Bernhardt; Florian Stock; Ilia Petrov 001; Andreas Koch 001 (ACM Trans. Reconfigurable Technol. Syst., 2025)

PUL: Pre-load in Software for Caches Wouldn't Always Play Along. - Arthur Bernhardt; Sajjad Tamimi; Florian Stock; Andreas Koch 001; Ilia Petrov 001 (CoRR, 2025)

CINDA: Using Cache-Coherent Interconnects for Accelerating Databases by Enabling Near-Data Processing of Update Transactions. - Sajjad Tamimi; Arthur Bernhardt; Florian Stock; Ilia Petrov 001; Andreas Koch 001 (IEEE Trans. Computers, 2025)

Reflecting on the Past 17 Years of Shingled Magnetic Recording for Insights Into Future Disk Transitions: A Survey. - Babar Khan; Andreas Koch 001 (ACM Trans. Storage, 2025)