Dynamic Speculation and Synchronization of Data Dependences. - Andreas Moshovos; Scott E. Breach; T. N. Vijaykumar; Gurindar S. Sohi (ISCA, 1997)

Streamlining Inter-Operation Memory Communication via Data Dependence Prediction. - Andreas Moshovos; Gurindar S. Sohi (MICRO, 1997)

Dependance Based Prefetching for Linked Data Structures. - Amir Roth; Andreas Moshovos; Gurindar S. Sohi (ASPLOS, 1998)

Improving virtual function call target prediction via dependence-based pre-computation. - Amir Roth; Andreas Moshovos; Gurindar S. Sohi (International Conference on Supercomputing, 1999)

Read-After-Read Memory Dependence Prediction. - Andreas Moshovos; Gurindar S. Sohi (MICRO, 1999)

Speculative Memory Cloaking and Bypassing. - Andreas Moshovos; Gurindar S. Sohi (Int. J. Parallel Program., 1999)

Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors. - Andreas Moshovos; Gurindar S. Sohi (HPCA, 2000)

CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit. - Zhi Alex Ye; Andreas Moshovos; Scott Hauck; Prithviraj Banerjee (ISCA, 2000)

Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors. - Amirali Baniasadi; Andreas Moshovos (MICRO, 2000)

Memory Dependence Prediction in Multimedia Applications. - Andreas Moshovos; Gurindar S. Sohi (J. Instr. Level Parallelism, 2000)

JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers. - Andreas Moshovos; Gokhan Memik; Babak Falsafi; Alok N. Choudhary (HPCA, 2001)

Slice-processors: an implementation of operation-based prediction. - Andreas Moshovos; Dionisios N. Pnevmatikatos; Amirali Baniasadi (ICS, 2001)

Instruction flow-based front-end throttling for power-aware high-performance processors. - Amirali Baniasadi; Andreas Moshovos (ISLPED, 2001)

Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling. - Andreas Moshovos; Gurindar S. Sohi (Proc. IEEE, 2001)

Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors. - Amirali Baniasadi; Andreas Moshovos (ICCD, 2002)

Asymmetric-frequency clustering: a power-aware back-end for high-performance processors. - Amirali Baniasadi; Andreas Moshovos (ISLPED, 2002)

Reducing Memory Latency via Read-after-Read Memory Dependence Prediction. - Andreas Moshovos; Gurindar S. Sohi (IEEE Trans. Computers, 2002)

Checkpointing alternatives for high performance, power-aware processors. - Andreas Moshovos (ISLPED, 2003)

Behavior and Performance of Interactive Multi-Player Game Servers. - Ahmed Abdelkhalek 002; Angelos Bilas; Andreas Moshovos (Clust. Comput., 2003)

Low-leakage asymmetric-cell SRAM. - Navid Azizi; Farid N. Najm; Andreas Moshovos (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Accurate and Complexity-Effective Spatial Pattern Prediction. - Chi F. Chen; Se-Hyun Yang; Babak Falsafi; Andreas Moshovos (HPCA, 2004)

SEPAS: a highly accurate energy-efficient branch predictor. - Amirali Baniasadi; Andreas Moshovos (ISLPED, 2004)

Memory State Compressors for Giga-Scale Checkpoint/Restore. - Andreas Moshovos; Alexandros Kostopoulos (IEEE PACT, 2005)

RECAST: Boosting Tag Line Buffer Coverage in Low-Power High-Level Caches "for Free". - Won-Ho Park; Andreas Moshovos; Babak Falsafi (ICCD, 2005)

RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence. - Andreas Moshovos (ISCA, 2005)

A Case for Asymmetric-Cell Cache Memories. - Andreas Moshovos; Babak Falsafi; Farid N. Najm; Navid Azizi (IEEE Trans. Very Large Scale Integr. Syst., 2005)

BranchTap: improving performance with very few checkpoints through adaptive speculation control. - Patrick Akl; Andreas Moshovos (ICS, 2006)

Spatial Memory Streaming. - Stephen Somogyi; Thomas F. Wenisch; Anastassia Ailamaki; Babak Falsafi; Andreas Moshovos (ISCA, 2006)

Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays. - Jason F. Cantin; James E. Smith 001; Mikko H. Lipasti; Andreas Moshovos; Babak Falsafi (IEEE Micro, 2006)

Mechanisms for store-wait-free multiprocessors. - Thomas F. Wenisch; Anastassia Ailamaki; Babak Falsafi; Andreas Moshovos (ISCA, 2007)

On the latency, energy and area of checkpointed, superscalar register alias tables. - Elham Safi; Patrick Akl; Andreas Moshovos; Andreas G. Veneris; Aggeliki Arapoyanni (ISLPED, 2007)

A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy. - Jason Zebchuk; Elham Safi; Andreas Moshovos (MICRO, 2007)

A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy. - Jason Zebchuk; Andreas Moshovos (IEEE Comput. Archit. Lett., 2007)

Predictor virtualization. - Ioana Burcea; Stephen Somogyi; Andreas Moshovos; Babak Falsafi (ASPLOS, 2008)

Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator. - Patrick Akl; Andreas Moshovos (HiPEAC, 2008)

Temporal streams in commercial server applications. - Thomas F. Wenisch; Michael Ferdman; Anastasia Ailamaki; Babak Falsafi; Andreas Moshovos (IISWC, 2008)

A physical level study and optimization of CAM-based checkpointed register alias table. - Elham Safi; Andreas Moshovos; Andreas G. Veneris (ISLPED, 2008)

Temporal instruction fetch streaming. - Michael Ferdman; Thomas F. Wenisch; Anastasia Ailamaki; Babak Falsafi; Andreas Moshovos (MICRO, 2008)

L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture. - Elham Safi; Andreas Moshovos; Andreas G. Veneris (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Phantom-BTB: a virtualized branch target buffer design. - Ioana Burcea; Andreas Moshovos (ASPLOS, 2009)

Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming. - Kaveh Aasaraai; Andreas Moshovos (FPL, 2009)

Practical off-chip meta-data for temporal memory streaming. - Thomas F. Wenisch; Michael Ferdman; Anastasia Ailamaki; Babak Falsafi; Andreas Moshovos (HPCA, 2009)

A tagless coherence directory. - Jason Zebchuk; Vijayalakshmi Srinivasan; Moinuddin K. Qureshi; Andreas Moshovos (MICRO, 2009)

A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors. - Elham Safi; Andreas Moshovos; Andreas G. Veneris (ICSAMOS, 2009)

Design space exploration of instruction schedulers for out-of-order soft processors. - Kaveh Aasaraai; Andreas Moshovos (FPT, 2010)

Demystifying GPU microarchitecture through microbenchmarking. - Henry Wong; Misel-Myrto Papadopoulou; Maryam Sadooghi-Alvandi; Andreas Moshovos (ISPASS, 2010)

An Efficient Non-blocking Data Cache for Soft Processors. - Kaveh Aasaraai; Andreas Moshovos (ReConFig, 2010)

Making Address-Correlated Prefetching Practical. - Thomas F. Wenisch; Michael Ferdman; Anastasia Ailamaki; Babak Falsafi; Andreas Moshovos (IEEE Micro, 2010)

On the Latency and Energy of Checkpointed Superscalar Register Alias Tables. - Elham Safi; Andreas Moshovos; Andreas G. Veneris (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Two-Stage, Pipelined Register Renaming. - Elham Safi; Andreas Moshovos; Andreas G. Veneris (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Pointy: a hybrid pointer prefetcher for managed runtime systems. - Ioana Burcea; Livio Soares; Andreas Moshovos (PACT, 2012)

ReCaP: a region-based cure for the common cold cache. - Jason Zebchuk; Harold W. Cain; Vijayalakshmi Srinivasan; Andreas Moshovos (PACT, 2012)

Reducing OLTP instruction misses with thread migration. - Islam Atta; Pinar Tözün; Anastasia Ailamaki; Andreas Moshovos (DaMoN, 2012)

Toward virtualizing branch direction prediction. - Maryam Sadooghi-Alvandi; Kaveh Aasaraai; Andreas Moshovos (DATE, 2012)

SLICC: Self-Assembly of Instruction Cache Collectives for OLTP Workloads. - Islam Atta; Pinar Tözün; Anastasia Ailamaki; Andreas Moshovos (MICRO, 2012)

SPREX: A soft processor with Runahead execution. - Kaveh Aasaraai; Andreas Moshovos (ReConFig, 2012)

NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution. - Kaveh Aasaraai; Andreas Moshovos (Int. J. Reconfigurable Comput., 2012)

A dual grain hit-miss detector for large die-stacked DRAM caches. - Michel El-Nacouzi; Islam Atta; Myrto Papadopoulou; Jason Zebchuk; Natalie D. Enright Jerger; Andreas Moshovos (DATE, 2013)

Characterizing the performance benefits of fused CPU/GPU systems using FusionSim. - Vitaly Zakharenko; Tor M. Aamodt; Andreas Moshovos (DATE, 2013)

Low-cost, high-performance branch predictors for soft processors. - Di Wu 006; Kaveh Aasaraai; Andreas Moshovos (FPL, 2013)

RECAP: A region-based cure for the common cold (cache). - Jason Zebchuk; Harold W. Cain; Xin Tong 005; Vijayalakshmi Srinivasan; Andreas Moshovos (HPCA, 2013)

STREX: boosting instruction cache reuse in OLTP workloads through stratified transaction execution. - Islam Atta; Pinar Tözün; Xin Tong 005; Anastasia Ailamaki; Andreas Moshovos (ISCA, 2013)

QTrace: An interface for customizable full system instrumentation. - Xin Tong 005; Jack Luo; Andreas Moshovos (ISPASS, 2013)

Multi-grain coherence directories. - Jason Zebchuk; Babak Falsafi; Andreas Moshovos (MICRO, 2013)

An Architectural Approach to Characterizing and Eliminating Sources of Inefficiency in a Soft Processor Design. - Kaveh Aasaraai; Andreas Moshovos (FCCM, 2014)

Image Signal Processors on FPGAs. - Di Wu 006; Andreas Moshovos (FCCM, 2014)

BarTLB: Barren page resistant TLB for managed runtime languages. - Xin Tong 005; Andreas Moshovos (ICCD, 2014)

Wormhole: Wisely Predicting Multidimensional Branches. - Jorge Albericio; Joshua San Miguel; Natalie D. Enright Jerger; Andreas Moshovos (MICRO, 2014)

What limits the operating frequency of a soft processor design. - Kaveh Aasaraai; Andreas Moshovos (ReConFig, 2014)

Advanced branch predictors for soft processors. - Di Wu 006; Andreas Moshovos (ReConFig, 2014)

Evaluating the memory system behavior of smartphone workloads. - Goran Narancic; Patrick Judd; Di Wu 006; Islam Atta; Michel Elnacouzi; Jason Zebchuk; Jorge Albericio; Natalie D. Enright Jerger; Andreas Moshovos; Kyros Kutulakos; Serag Gadelrab (ICSAMOS, 2014)

ADDICT: Advanced Instruction Chasing for Transactions. - Pinar Tözün; Islam Atta; Anastasia Ailamaki; Andreas Moshovos (Proc. VLDB Endow., 2014)

Optimizing Memory Translation Emulation in Full System Emulators. - Xin Tong 005; Toshihiko Koju; Motohiro Kawahito; Andreas Moshovos (ACM Trans. Archit. Code Optim., 2014)

Prediction-based superpage-friendly TLB designs. - Misel-Myrto Papadopoulou; Xin Tong 005; André Seznec; Andreas Moshovos (HPCA, 2015)

QTrace: a framework for customizable full system instrumentation. - Xin Tong 005; Andreas Moshovos (ISPASS, 2015)

Self-contained, accurate precomputation prefetching. - Islam Atta; Xin Tong 005; Vijayalakshmi Srinivasan; Ioana Baldini; Andreas Moshovos (MICRO, 2015)

Doppelgänger: a cache for approximate computing. - Joshua San Miguel; Jorge Albericio; Andreas Moshovos; Natalie D. Enright Jerger (MICRO, 2015)

Reduced-Precision Strategies for Bounded Memory in Deep Neural Nets. - Patrick Judd; Jorge Albericio; Tayler H. Hetherington; Tor M. Aamodt; Natalie D. Enright Jerger; Raquel Urtasun; Andreas Moshovos (CoRR, 2015)

Proteus: Exploiting Numerical Precision Variability in Deep Neural Networks. - Patrick Judd; Jorge Albericio; Tayler H. Hetherington; Tor M. Aamodt; Natalie D. Enright Jerger; Andreas Moshovos (ICS, 2016)

Memory controller design under cloud workloads. - Mostafa Mahmoud; Andreas Moshovos (IISWC, 2016)

Cnvlutin: Ineffectual-Neuron-Free Deep Neural Network Computing. - Jorge Albericio; Patrick Judd; Tayler H. Hetherington; Tor M. Aamodt; Natalie D. Enright Jerger; Andreas Moshovos (ISCA, 2016)

Message from the program chair. - Andreas Moshovos (ISPASS, 2016)

Stripes: Bit-serial deep neural network computing. - Patrick Judd; Jorge Albericio; Tayler H. Hetherington; Tor M. Aamodt; Andreas Moshovos (MICRO, 2016)

Bit-Pragmatic Deep Neural Network Computing. - Jorge Albericio; Patrick Judd; Alberto Delmas; Sayeh Sharify; Andreas Moshovos (ICLR (Workshop), 2017)

Bit-pragmatic deep neural network computing. - Jorge Albericio; Alberto Delmas; Patrick Judd; Sayeh Sharify; Gerard O'Leary; Roman Genov; Andreas Moshovos (MICRO, 2017)

IDEAL: image denoising accelerator. - Mostafa Mahmoud; Bojian Zheng; Alberto Delmas Lascorz; Felix Heide; Jonathan Assouline; Paul Boucher; Emmanuel Onzon; Andreas Moshovos (MICRO, 2017)

Stripes: Bit-Serial Deep Neural Network Computing. - Patrick Judd; Jorge Albericio; Andreas Moshovos (IEEE Comput. Archit. Lett., 2017)

Dynamic Stripes: Exploiting the Dynamic Precision Requirements of Activation Values in Neural Networks. - Alberto Delmas; Patrick Judd; Sayeh Sharify; Andreas Moshovos (CoRR, 2017)

Tartan: Accelerating Fully-Connected and Convolutional Layers in Deep Learning Networks by Exploiting Numerical Precision Variability. - Alberto Delmas; Sayeh Sharify; Patrick Judd; Andreas Moshovos (CoRR, 2017)

Cnvlutin2: Ineffectual-Activation-and-Weight-Free Deep Neural Network Computing. - Patrick Judd; Alberto Delmas Lascorz; Sayeh Sharify; Andreas Moshovos (CoRR, 2017)

Loom: Exploiting Weight and Activation Precisions to Accelerate Convolutional Neural Networks. - Sayeh Sharify; Alberto Delmas Lascorz; Patrick Judd; Andreas Moshovos (CoRR, 2017)

Loom: exploiting weight and activation precisions to accelerate convolutional neural networks. - Sayeh Sharify; Alberto Delmas Lascorz; Kevin Siu; Patrick Judd; Andreas Moshovos (DAC, 2018)

Characterizing Sources of Ineffectual Computations in Deep Learning Networks. - Milos Nikolic 002; Mostafa Mahmoud; Andreas Moshovos (IISWC, 2018)

Gene Sequencing: Where Time Goes. - Meysam Roodi; Andreas Moshovos (IISWC, 2018)

Memory Requirements for Convolutional Neural Network Hardware Accelerators. - Kevin Siu; Dylan Malone Stuart; Mostafa Mahmoud; Andreas Moshovos (IISWC, 2018)

Diffy: a Déjà vu-Free Differential Deep Neural Network Accelerator. - Mostafa Mahmoud; Kevin Siu; Andreas Moshovos (MICRO, 2018)

Value-Based Deep Learning Hardware Acceleration. - Andreas Moshovos (NoCArc@MICRO, 2018)

Identifying and Exploiting Ineffectual Computations to Enable Hardware Acceleration of Deep Learning. - Andreas Moshovos; Jorge Albericio; Patrick Judd; Alberto Delmas; Sayeh Sharify; Mostafa Mahmoud; Tayler H. Hetherington; Milos Nikolic 002; Dylan Malone Stuart; Kevin Siu; Zissis Poulos; Tor M. Aamodt; et al. (NEWCAS, 2018)

Exploiting Typical Values to Accelerate Deep Learning. - Andreas Moshovos; Jorge Albericio; Patrick Judd; Alberto Delmas Lascorz; Sayeh Sharify; Zissis Poulos; Tayler H. Hetherington; Tor M. Aamodt; Natalie D. Enright Jerger (Computer, 2018)

Bit-Tactical: Exploiting Ineffectual Computations in Convolutional Neural Networks: Which, Why, and How. - Alberto Delmas; Patrick Judd; Dylan Malone Stuart; Zissis Poulos; Mostafa Mahmoud; Sayeh Sharify; Milos Nikolic 002; Andreas Moshovos (CoRR, 2018)

DPRed: Making Typical Activation Values Matter In Deep Learning Computing. - Alberto Delmas; Sayeh Sharify; Patrick Judd; Milos Nikolic 002; Andreas Moshovos (CoRR, 2018)

Laconic Deep Learning Computing. - Sayeh Sharify; Mostafa Mahmoud; Alberto Delmas Lascorz; Milos Nikolic 002; Andreas Moshovos (CoRR, 2018)

Value-Based Deep-Learning Acceleration. - Andreas Moshovos; Jorge Albericio; Patrick Judd; Alberto Delmas Lascorz; Sayeh Sharify; Tayler H. Hetherington; Tor M. Aamodt; Natalie D. Enright Jerger (IEEE Micro, 2018)

Proteus: Exploiting precision variability in deep neural networks. - Patrick Judd; Jorge Albericio; Tayler H. Hetherington; Tor M. Aamodt; Natalie D. Enright Jerger; Raquel Urtasun; Andreas Moshovos (Parallel Comput., 2018)

Bit-Tactical: A Software/Hardware Approach to Exploiting Value and Bit Sparsity in Neural Networks. - Alberto Delmas Lascorz; Patrick Judd; Dylan Malone Stuart; Zissis Poulos; Mostafa Mahmoud; Sayeh Sharify; Milos Nikolic 002; Kevin Siu; Andreas Moshovos (ASPLOS, 2019)

BWA-MEM Performance: Suffix Array Storage Size. - Meysam Roodi; Zahra Lak; Andreas Moshovos (BHI, 2019)

MemAlign: A Memory Structure to Accelerate Gene Sequencing. - Meysam Roodi; Andreas Moshovos (BIBE, 2019)

SW+: On Accelerating Smith-Waterman Execution of GATK HaplotypeCaller. - Meysam Roodi; Andreas Moshovos (CIBB, 2019)

Deep Learning Language Modeling Workloads: Where Time Goes on Graphics Processors. - Ali Hadi Zadeh; Zissis Poulos; Andreas Moshovos (IISWC, 2019)

Laconic deep learning inference acceleration. - Sayeh Sharify; Alberto Delmas Lascorz; Mostafa Mahmoud; Milos Nikolic 002; Kevin Siu; Dylan Malone Stuart; Zissis Poulos; Andreas Moshovos (ISCA, 2019)

Characterizing Sources of Ineffectual Computations in Deep Learning Networks. - Milos Nikolic 002; Mostafa Mahmoud; Andreas Moshovos; Yiren Zhao; Robert D. Mullins (ISPASS, 2019)

ShapeShifter: Enabling Fine-Grain Data Width Adaptation in Deep Learning. - Alberto Delmas Lascorz; Sayeh Sharify; Isak Edo Vivancos; Dylan Malone Stuart; Omar Mohamed Awad; Patrick Judd; Mostafa Mahmoud; Milos Nikolic 002; Kevin Siu; Zissis Poulos; Andreas Moshovos (MICRO, 2019)

Training CNNs faster with Dynamic Input and Kernel Downsampling. - Zissis Poulos; Ali Nouri; Andreas Moshovos (CoRR, 2019)

Accelerating Image-Sensor-Based Deep Learning Applications. - Mostafa Mahmoud; Dylan Malone Stuart; Zissis Poulos; Alberto Delmas Lascorz; Patrick Judd; Sayeh Sharify; Milos Nikolic 002; Kevin Siu; Isak Edo Vivancos; Jorge Albericio; Andreas Moshovos (IEEE Micro, 2019)

Late Breaking Results: Building an On-Chip Deep Learning Memory Hierarchy Brick by Brick. - Isak Edo Vivancos; Sayeh Sharify; Milos Nikolic 002; Ciaran Bannon; Mostafa Mahmoud; Alberto Delmas Lascorz; Andreas Moshovos (DAC, 2020)

TensorDash: Exploiting Sparsity to Accelerate Deep Neural Network Training. - Mostafa Mahmoud; Isak Edo; Ali Hadi Zadeh; Omar Mohamed Awad; Gennady Pekhimenko; Jorge Albericio; Andreas Moshovos (MICRO, 2020)

GOBO: Quantizing Attention-Based NLP Models for Low Latency and Energy Efficient Inference. - Ali Hadi Zadeh; Isak Edo; Omar Mohamed Awad; Andreas Moshovos (MICRO, 2020)

BitPruning: Learning Bitlengths for Aggressive and Accurate Quantization. - Milos Nikolic 002; Ghouthi Boukli Hacene; Ciaran Bannon; Alberto Delmas Lascorz; Matthieu Courbariaux; Yoshua Bengio; Vincent Gripon; Andreas Moshovos (CoRR, 2020)

GOBO: Quantizing Attention-Based NLP Models for Low Latency and Energy Efficient Inference. - Ali Hadi Zadeh; Andreas Moshovos (CoRR, 2020)

TensorDash: Exploiting Sparsity to Accelerate Deep Neural Network Training and Inference. - Mostafa Mahmoud; Isak Edo Vivancos; Ali Hadi Zadeh; Omar Mohamed Awad; Gennady Pekhimenko; Jorge Albericio; Andreas Moshovos (CoRR, 2020)

Noema: Hardware-Efficient Template Matching for Neural Population Pattern Detection. - Ameer M. S. Abdelhadi; Eugene Sha; Ciaran Bannon; Hendrik Steenland; Andreas Moshovos (MICRO, 2021)

FPRaker: A Processing Element For Accelerating Neural Network Training. - Omar Mohamed Awad; Mostafa Mahmoud; Isak Edo; Ali Hadi Zadeh; Ciaran Bannon; Anand Jayarajan; Gennady Pekhimenko; Andreas Moshovos (MICRO, 2021)

Boveda: Building an On-Chip Deep Learning Memory Hierarchy Brick by Brick. - Isak Edo Vivancos; Sayeh Sharify; Daniel Ly-Ma; Ameer Abdelhadi; Ciaran Bannon; Milos Nikolic 002; Mostafa Mahmoud; Alberto Delmas Lascorz; Gennady Pekhimenko; Andreas Moshovos (MLSys, 2021)

A Massive-Scale Brain Activity Decoding Chip. - Ameer Abdelhadi; Eugene Sha; Andreas Moshovos (HCS, 2022)

Mokey: enabling narrow fixed-point inference for out-of-the-box floating-point transformer models. - Ali Hadi Zadeh; Mostafa Mahmoud; Ameer Abdelhadi; Andreas Moshovos (ISCA, 2022)

A 39, 000 Subexposures/s CMOS Image Sensor with Dual-tap Coded-exposure Data-memory Pixel for Adaptive Single-shot Computational Imaging. - Rahul Gulve; Navid Sarhangnejad; Gairik Dutta; Motasem Sakr; Don Nguyen; Roberto Rangel; Wenzheng Chen; Zhengfan Xia; Mian Wei; Nikita Gusev; Esther Y. H. Lin; Xiaonong Sun; et al. (VLSI Technology and Circuits, 2022)

APack: Off-Chip, Lossless Data Compression for Efficient Deep Learning Inference. - Alberto Delmas Lascorz; Mostafa Mahmoud; Andreas Moshovos (CoRR, 2022)

Schrödinger's FP: Dynamic Adaptation of Floating-Point Containers for Deep Learning Training. - Milos Nikolic 002; Enrique Torres-Sánchez; Jiahui Wang; Ali Hadi Zadeh; Mostafa Mahmoud; Ameer Abdelhadi; Andreas Moshovos (CoRR, 2022)

cuSCNN : an Efficient CUDA Implementation of Sparse CNNs. - Mohamed A. Elgammal; Omar Mohamed Awad; Isak Edo Vivancos; Andreas Moshovos; Vaughn Betz (HEART, 2023)

39 000-Subexposures/s Dual-ADC CMOS Image Sensor With Dual-Tap Coded-Exposure Pixels for Single-Shot HDR and 3-D Computational Imaging. - Rahul Gulve; Navid Sarhangnejad; Gairik Dutta; Motasem Sakr; Don Nguyen; Roberto Rangel; Wenzheng Chen; Zhengfan Xia; Mian Wei; Nikita Gusev; Esther Y. H. Lin; Xiaonong Sun; et al. (IEEE J. Solid State Circuits, 2023)

Every Bit Matters: A Hardware/Software Approach for Enabling More Powerful Machine Learning Models. - Enrique Torres-Sánchez; Milos Nikolic 002; Kareem Ibrahim; Alberto Delmas Lascorz; Ali Hadi Zadeh; Jiahui Wang; Ameer Abdelhadi; Mostafa Mahmoud; Christina Giannoula; Andreas Moshovos (IEEECONF, 2024)

Atalanta: A Bit is Worth a "Thousand" Tensor Values. - Alberto Delmas Lascorz; Mostafa Mahmoud; Ali Hadi Zadeh; Milos Nikolic 002; Kareem Ibrahim; Christina Giannoula; Ameer Abdelhadi; Andreas Moshovos (ASPLOS (2), 2024)

Marple: Scalable Spike Sorting for Untethered Brain-Machine Interfacing. - Eugene Sha; Andy Liu; Kareem Ibrahim; Mostafa Mahmoud; Christina Giannoula; Ameer Abdelhadi; Andreas Moshovos (ASPLOS (2), 2024)

Low-Bitwidth Floating Point Quantization for Efficient High-Quality Diffusion Models. - Cheng Chen; Christina Giannoula; Andreas Moshovos (IISWC, 2024)

BitPruning: Learning Bitlengths for Aggressive and Accurate Quantization. - Milos Nikolic 002; Ghouthi Boukli Hacene; Ciaran Bannon; Alberto Delmas Lascorz; Matthieu Courbariaux; Omar Mohamed Awad; Isak Edo Vivancos; Yoshua Bengio; Vincent Gripon; Andreas Moshovos (ISCAS, 2024)

Schrodinger's FP Training Neural Networks with Dynamic Floating-Point Containers. - Milos Nikolic 002; Enrique Torres-Sánchez; Jiahui Wang; Ali Hadi Zadeh; Mostafa Mahmoud; Ameer Abdelhadi; Kareem Ibrahim; Andreas Moshovos (MLSys, 2024)