Can the advantages of RISC be utilized in real time systems? - Andreas Steininger; Herbert Schweinzer (RTS, 1991)

Towards an optimal combination of error detection mechanisms. - Andreas Steininger; Herbert Schweinzer (Microprocessing and Microprogramming, 1991)

The design of a fail-silent processing node for the predictable hard real-time system MARS. - Johannes Reisinger; Andreas Steininger (Distributed Syst. Eng., 1993)

A Model for the Analysis of the Fault Injection Process. - Andreas Steininger; Herbert Schweinzer (FTCS, 1995)

On Finding an Optimal Combination of Error Detection Mechanisms Based on Results of Fault Injection Experiments. - Andreas Steininger; Christoph Scherrer (FTCS, 1997)

On the Necessity of On-Line-BIST in Safety-Critical Applications - A Case Study. - Andreas Steininger; Christoph Scherrer (FTCS, 1999)

Economic Online Self-Test in the Time-Triggered Architecture. - Andreas Steininger; Christopher Temple (IEEE Des. Test Comput., 1999)

On the determination of dynamic errors for rise time measurement with an oscilloscope. - Christoph Mittermayer; Andreas Steininger (IEEE Trans. Instrum. Meas., 1999)

How Does Resource Utilization Affect Fault Tolerance? - Andreas Steininger; Christoph Scherrer (DFT, 2000)

Testing and built-in self-test - A survey. - Andreas Steininger (J. Syst. Archit., 2000)

How to Tune the MTTF of a Fail-Silent System. - Andreas Steininger; Christoph Scherrer (DFT, 2001)

Using Offline and Online BIST to Improve System Dependability - The TTPC-C Example. - Andreas Steininger; Johann Vilanek (ICCD, 2002)

Identifying Efficient Combinations of Error Detection Mechanisms Based on Results of Fault Injection Experiments. - Andreas Steininger; Christoph Scherrer (IEEE Trans. Computers, 2002)

Processor Support for Temporal Predictability - The SPEAR Design Example. - Martin Delvai; Wolfgang Huber; Peter P. Puschner; Andreas Steininger (ECRTS, 2003)

Built-In Fault Injectors - The Logical Continuation of BIST? - Andreas Steininger; Babak Rahbaran; Thomas Handl (WISES, 2003)

Dealing with dormant faults in an embedded fault-tolerant computer system. - Christoph Scherrer; Andreas Steininger (IEEE Trans. Reliab., 2003)

A transparent online memory test for simultaneous detection of functional faults and soft errors in memories. - Karl Thaller; Andreas Steininger (IEEE Trans. Reliab., 2003)

Built-in Fault Injection in Hardware - The FIDYCO Example. - Babak Rahbaran; Andreas Steininger; Thomas Handl (DELTA, 2004)

Embedded Real-Time-Tracer - An Approach with IDE. - Babak Rahbaran; Matthias Függer; Andreas Steininger (WISES, 2004)

A Generic Dual Core Architecture with Error Containment. - Thomas Kottke; Andreas Steininger (Comput. Artif. Intell., 2004)

Efficient stimulus generation for testing embedded distributed systems the FlexRay example. - Eric Armengaud; Andreas Steininger; Martin Horauer (ETFA, 2005)

A structured approach for the systematic test of embedded automotive communication systems. - Eric Armengaud; Florian Rothensteiner; Andreas Steininger; Roman Pallierer; Martin Horauer; Martin Zauner (ITC, 2005)

VLSI Implementation of a Fault-Tolerant Distributed Clock Generation. - Markus Ferringer; Gottfried Fuchs; Andreas Steininger; Gerald Kempf (DFT, 2006)

Recovery Mechanisms for Dual Core Architectures. - Christian El Salloum; Andreas Steininger; Peter Tummeltshammer; Werner Harter (DFT, 2006)

Solving the Fundamental Problem of Digital Design - A Systematic Review of Design Methods. - Martin Delvai; Andreas Steininger (DSD, 2006)

A Reconfigurable Generic Dual-Core Architecture. - Thomas Kottke; Andreas Steininger (DSN, 2006)

Automatic Parameter Identi cation in FlexRay based Automotive Communication Networks. - Eric Armengaud; Andreas Steininger; Martin Horauer (ETFA, 2006)

Hardware implementation of an SAD based stereo vision algorithm. - Kristian Ambrosch; Wilfried Kubinger; Martin Humenberger; Andreas Steininger (CVPR, 2007)

The effect of quartz drift on convergence-average based clock synchronization. - Eric Armengaud; Andreas Steininger; Alexander Hanzlik (ETFA, 2007)

A Fail-Silent Reconfigurable Superscalar Processor. - Thomas Kottke; Andreas Steininger (PRDC, 2007)

FIT-IT-Projekt DARTS: dezentrale fehlertolerante Taktgenerierung. - Ulrich Schmid 001; Andreas Steininger; Manfred Sust (Elektrotech. Informationstechnik, 2007)

Extending two non-parametric transforms for FPGA based stereo matching using bayer filtered cameras. - Kristian Ambrosch; Martin Humenberger; Wilfried Kubinger; Andreas Steininger (CVPR Workshops, 2008)

Error Containment in the Presence of Metastability. - Andreas Steininger (Fault-Tolerant Distributed Algorithms on VLSI Chips, 2008)

Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks. - Paul Milbredt; Andreas Steininger; Martin Horauer (DELTA, 2008)

Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip. - Gottfried Fuchs; Matthias Függer; Ulrich Schmid 001; Andreas Steininger (DSD, 2008)

Automated generation of explicit connectors for component based hardware/software interaction in embedded real-time systems. - Wolfgang Forster; Christof Kutschera; Andreas Steininger; Karl M. Göschka (IPDPS, 2008)

An investigation of the clique problem in FlexRay. - Paul Milbredt; Martin Horauer; Andreas Steininger (SIES, 2008)

Flexible Hardware-Based Stereo Matching. - Kristian Ambrosch; Wilfried Kubinger; Martin Humenberger; Andreas Steininger (EURASIP J. Embed. Syst., 2008)

Towards a Systematic Test for Embedded Automotive Communication Systems. - Eric Armengaud; Andreas Steininger; Martin Horauer (IEEE Trans. Ind. Informatics, 2008)

On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme. - Gottfried Fuchs; Matthias Függer; Andreas Steininger (ASYNC, 2009)

Remote measurement of local oscillator drifts in FlexRay networks. - Eric Armengaud; Andreas Steininger (DATE, 2009)

On the role of the power supply as an entry for common cause faults - An experimental analysis. - Peter Tummeltshammer; Andreas Steininger (DDECS, 2009)

Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic. - Werner Friesenbichler; Andreas Steininger (DSD, 2009)

On the Risk of Fault Coupling over the Chip Substrate. - Peter Tummeltshammer; Andreas Steininger (DSD, 2009)

Power supply induced common cause faults-experimental assessment of potential countermeasures. - Peter Tummeltshammer; Andreas Steininger (DSN, 2009)

A Metastability-Free Multi-synchronous Communication Scheme for SoCs. - Thomas Polzer; Thomas Handl; Andreas Steininger (SSS, 2009)

Is Asynchronous Logic More Robust Than Synchronous Logic?. - Babak Rahbaran; Andreas Steininger (IEEE Trans. Dependable Secur. Comput., 2009)

Safely Stimulating the Clock Synchronization Algorithm in Time-Triggered Systems - a Combined Formal & Experimental Approach. - Matthias Függer; Eric Armengaud; Andreas Steininger (IEEE Trans. Ind. Informatics, 2009)

Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study. - Thomas Panhofer; Werner Friesenbichler; Andreas Steininger (AHS, 2010)

A deterministic approach for hardware fault injection in asynchronous QDI logic. - Werner Friesenbichler; Thomas Panhofer; Andreas Steininger (DDECS, 2010)

Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. - Marcus Jeitler; Jakob Lechner; Andreas Steininger (DDECS, 2010)

Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm. - Thomas Panhofer; Werner Friesenbichler; Andreas Steininger (DSN Workshops, 2010)

Test-Case Generation for Embedded Binary Code Using Abstract Interpretation. - Thomas Reinbacher; Jörg Brauer; Martin Horauer; Andreas Steininger; Stefan Kowalewski (MEMICS, 2010)

Past Time LTL Runtime Verification for Microcontroller Binary Code. - Thomas Reinbacher; Jörg Brauer; Martin Horauer; Andreas Steininger; Stefan Kowalewski (FMICS, 2011)

Automated Test-Trace Inspection for Microcontroller Binary Code. - Thomas Reinbacher; Jörg Brauer; Daniel Schachinger; Andreas Steininger; Stefan Kowalewski (RV, 2011)

Replicated processors on a single die - How independently do they fail? - Peter Tummeltshammer; Andreas Steininger (Elektrotech. Informationstechnik, 2011)

VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation. - Gottfried Fuchs; Andreas Steininger (J. Electr. Comput. Eng., 2011)

Designing FlexRay-based automotive architectures: A holistic OEM approach. - Paul Milbredt; Michael Glaß; Martin Lukasiewycz; Andreas Steininger; Jürgen Teich (DATE, 2012)

Radiation-tolerant combinational gates - an implementation based comparison. - Varadan Savulimedu Veeravalli; Andreas Steininger (DDECS, 2012)

Protecting an Asynchronous NoC against Transient Channel Faults. - Syed Rameez Naqvi; Varadan Savulimedu Veeravalli; Andreas Steininger (DSD, 2012)

Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. - Varadan Savulimedu Veeravalli; Thomas Polzer; Andreas Steininger; Ulrich Schmid 001 (DSD, 2012)

Muller C-Element Metastability Containment. - Thomas Polzer; Andreas Steininger; Jakob Lechner (PATMOS, 2012)

FATAL+: A Self-Stabilizing Byzantine Fault-tolerant Clocking Scheme for SoCs - Danny Dolev; Matthias Függer; Christoph Lenzen 001; Markus Posch; Ulrich Schmid 001; Andreas Steininger (CoRR, 2012)

Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs. - Robert Najvirt; Syed Rameez Naqvi; Andreas Steininger (ASYNC, 2013)

An SET Tolerant Tree Arbiter Cell. - Syed Rameez Naqvi; Andreas Steininger; Jakob Lechner (ASYNC, 2013)

An Approach for Efficient Metastability Characterization of FPGAs through the Designer. - Thomas Polzer; Andreas Steininger (ASYNC, 2013)

A Multi-Credit Flow Control scheme for asynchronous NoCs. - Syed Rameez Naqvi; Robert Najvirt; Andreas Steininger (DDECS, 2013)

Digital Late-Transition Metastability Simulation Model. - Thomas Polzer; Andreas Steininger (DSD, 2013)

SET propagation in micropipelines. - Thomas Polzer; Andreas Steininger (PATMOS, 2013)

Metastability characterization for muller C-elements. - Thomas Polzer; Andreas Steininger (PATMOS, 2013)

Software Composability and Mixed Criticality for Triple Modular Redundant Architectures. - Stefan Resch; Andreas Steininger; Christoph Scherrer (SASSUR@SAFECOMP, 2013)

An infrastructure for accurate characterization of single-event transients in digital circuits. - Varadan Savulimedu Veeravalli; Thomas Polzer; Ulrich Schmid 001; Andreas Steininger; Michael Hofbauer; Kurt Schweiger; Horst Dietrich; Kerstin Schneider-Hornstein; Horst Zimmermann; Kay-Obbe Voss; Bruno Merk; Michael Hajek (Microprocess. Microsystems, 2013)

A tree arbiter cell for high speed resource sharing in asynchronous environments. - Syed Rameez Naqvi; Andreas Steininger (DATE, 2014)

Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic. - Jürgen Maier 002; Andreas Steininger (DDECS, 2014)

Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. - Andreas Steininger; Varadan Savulimedu Veeravalli; Dan Alexandrescu; Enrico Costenaro; Lorena Anghel (ICCD, 2014)

Protection of Muller-Pipelines from transient faults. - Syed Rameez Naqvi; Jakob Lechner; Andreas Steininger (ISQED, 2014)

Architecture for monitoring SET propagation in 16-bit Sklansky adder. - Varadan Savulimedu Veeravalli; Andreas Steininger (ISQED, 2014)

Measuring SET pulsewidths in logic gates using digital infrastructure. - Varadan Savulimedu Veeravalli; Andreas Steininger; Ulrich Schmid 001 (ISQED, 2014)

Equivalence of clock gating and synchronization with applicability to GALS communication. - Robert Najvirt; Andreas Steininger (PATMOS, 2014)

Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip. - Danny Dolev; Matthias Függer; Markus Posch; Ulrich Schmid 001; Andreas Steininger; Christoph Lenzen 001 (J. Comput. Syst. Sci., 2014)

Runtime verification of microcontroller binary code. - Thomas Reinbacher; Jörg Brauer; Martin Horauer; Andreas Steininger; Stefan Kowalewski (Sci. Comput. Program., 2014)

How to Synchronize a Pausible Clock to a Reference. - Robert Najvirt; Andreas Steininger (ASYNC, 2015)

Containment of Metastable Voltages in FPGAs. - Robert Najvirt; Thomas Polzer; Florian Beck; Andreas Steininger (DDECS, 2015)

Measuring the Distribution of Metastable Upsets over Time. - Thomas Polzer; Andreas Steininger (DSD, 2015)

Enhanced Metastability Characterization Based on AC Analysis. - Thomas Polzer; Andreas Steininger (DSD, 2015)

Reliable and Continuous Measurement of SET Pulse Widths. - Varadan Savulimedu Veeravalli; Andreas Steininger (DSD, 2015)

A pausible clock with crystal oscillator accuracy. - Robert Najvirt; Andreas Steininger (ECCTD, 2015)

Methods for analysing and improving the fault resilience of delay-insensitive codes. - Jakob Lechner; Andreas Steininger; Florian Huemer (ICCD, 2015)

A versatile and reliable glitch filter for clocks. - Robert Najvirt; Andreas Steininger (PATMOS, 2015)

Fault-tolerant Distributed Systems in Hardware. - Danny Dolev; Matthias Függer; Christoph Lenzen 001; Ulrich Schmid 001; Andreas Steininger (Bull. EATCS, 2015)

Digitale Mikroelektronik in Österreich. - Peter Rössler; Andreas Steininger (Elektrotech. Informationstechnik, 2015)

Building reliable systems-on-chip in nanoscale technologies. - Andreas Steininger; Horst Zimmermann; Axel Jantsch; Michael Hofbauer; Ulrich Schmid 001; Kurt Schweiger; Varadan Savulimedu Veeravalli (Elektrotech. Informationstechnik, 2015)

A composable real-time architecture for replicated railway applications. - Stefan Resch; Andreas Steininger; Christoph Scherrer (J. Syst. Archit., 2015)

The Metastable Behavior of a Schmitt-Trigger. - Andreas Steininger; Jürgen Maier 002; Robert Najvirt (ASYNC, 2016)

A general approach for comparing metastable behavior of digital CMOS gates. - Thomas Polzer; Andreas Steininger (DDECS, 2016)

Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? - Andreas Steininger; Robert Najvirt; Jürgen Maier 002 (DSD, 2016)

Design and Physical Implementation of a Target ASIC for SET Experiments. - Varadan Savulimedu Veeravalli; Andreas Steininger (DSD, 2016)

Study of a delayed single-event effect in the Muller C-element. - Varadan Savulimedu Veeravalli; Andreas Steininger (ETS, 2016)

A new coding scheme for fault tolerant 4-phase delay-insensitive codes. - Florian Huemer; Jakob Lechner; Andreas Steininger (ICCD, 2016)

On the Appropriate Handling of Metastable Voltages in FPGAs. - Thomas Polzer; Robert Najvirt; Florian Beck; Andreas Steininger (J. Circuits Syst. Comput., 2016)

Measuring Metastability with Free-Running Clocks. - Robert Najvirt; Thomas Polzer; Andreas Steininger (ASYNC, 2017)

A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study. - Marko S. Andjelkovic; Milos Krstic; Rolf Kraemer; Varadan Savulimedu Veeravalli; Andreas Steininger (ATS, 2017)

Measuring metastability using a time-to-digital converter. - Thomas Polzer; Florian Huemer; Andreas Steininger (DDECS, 2017)

Setup for an Experimental Study of Radiation Effects in 65nm CMOS. - Bernhard Fritz; Andreas Steininger; Václav Simek; Varadan Savulimedu Veeravalli (DSD, 2017)

A Model for the Metastability Delay of Sequential Elements. - Thomas Polzer; Andreas Steininger (J. Circuits Syst. Comput., 2017)

Foreword. - Andreas Steininger; Adam Pawlak; Viera Stopjaková (J. Circuits Syst. Comput., 2017)

A versatile architecture for long-term monitoring of single-event transient durations. - Varadan Savulimedu Veeravalli; Andreas Steininger; Ulrich Schmid 001 (Microprocess. Microsystems, 2017)

Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication. - Florian Huemer; Andreas Steininger (ASYNC, 2018)

Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. - Florian Huemer; Thomas Polzer; Andreas Steininger (DDECS, 2018)

State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. - Markus Schütz; Andreas Steininger; Florian Huemer; Jakob Lechner (DFT, 2018)

Refined metastability characterization using a time-to-digital converter. - Thomas Polzer; Florian Huemer; Andreas Steininger (Microelectron. Reliab., 2018)

Efficient Metastability Characterization for Schmitt-Triggers. - Jürgen Maier 002; Andreas Steininger (ASYNC, 2019)

Sustainable Security & Safety: Challenges and Opportunities. - Andrew Paverd; Marcus Völp; Ferdinand Brasser; Matthias Schunter; N. Asokan; Ahmad-Reza Sadeghi; Paulo Jorge Esteves Veríssimo; Andreas Steininger; Thorsten Holz (CERTS, 2019)

International Symposium on Design and Diagnostics of Electronic Circuits and Systems. - Zoran Stamenkovic; Alberto Bosio; György Cserey; Ondrej Novák; Witold A. Pleskacz; Lukás Sekanina; Andreas Steininger; Goran Stojanovic; Viera Stopjaková (ITC, 2019)

An Experimental Study of Metastability-Induced Glitching Behavior. - Thomas Polzer; Florian Huemer; Andreas Steininger (J. Circuits Syst. Comput., 2019)

Timing Domain Crossing using Muller Pipelines. - Florian Huemer; Andreas Steininger (ASYNC, 2020)

Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock. - Wolfgang Duer; Andreas Steininger (DDECS, 2020)

On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective. - Raghda El Shehaby; Andreas Steininger (ICCD, 2020)

Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. - Patrick Behal; Florian Huemer; Robert Najvirt; Andreas Steininger; Zaheer Tabassam (ASYNC, 2021)

Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines. - Raghda El Shehaby; Andreas Steininger (DDECS, 2021)

An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. - Patrick Behal; Florian Huemer; Robert Najvirt; Andreas Steininger (DSD, 2021)

On SAT-Based Model Checking of Speed-Independent Circuits. - Florian Huemer; Robert Najvirt; Andreas Steininger (DDECS, 2022)

AµFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages. - Zaheer Tabassam; Syed Rameez Naqvi; Andreas Steininger (DDECS, 2022)

Study and Comparison of QDI Pipeline Components' Sensitivity to Permanent Faults. - Raghda El Shehaby; Andreas Steininger (DFT, 2022)

SET Hardened Derivatives of QDI Buffer Template. - Zaheer Tabassam; Andreas Steininger (DFT, 2022)

Towards Resilient QDI Pipeline Implementations. - Zaheer Tabassam; Andreas Steininger (DSD, 2022)

enpheeph: A Fault Injection Framework for Spiking and Compressed Deep Neural Networks. - Alessio Colucci; Andreas Steininger; Muhammad Shafique 001 (IROS, 2022)

ATLAS: An IoT Architecture and Secure Open-source Networking Stack for Anonymous Localization and Tracking Using Smartphones and Bluetooth Beacons. - Bharath Srinivas Prabakaran; Felix Fasching; Juri Schreib; Andreas Steininger; Muhammad Shafique 001 (CoRR, 2022)

Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses. - Jürgen Maier 002; Christian Hartl-Nesic; Andreas Steininger (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic. - Zaheer Tabassam; Andreas Steininger; Robert Najvirt; Florian Huemer (ASYNC, 2023)

Towards Resilient Quasi Delay Insensitive Conditional Control Elements. - Zaheer Tabassam; Andreas Steininger (DSD, 2023)

SET Effects on Quasi Delay Insensitive and Synchronous Circuits. - Zaheer Tabassam; Andreas Steininger (ETS, 2023)

On the Susceptibility of QDI Circuits to Transient Faults. - Raghda El Shehaby; Matthias Függer; Andreas Steininger (FORMATS, 2023)

SHIELD: An Adaptive and Lightweight Defense against the Remote Power Side-Channel Attacks on Multi-tenant FPGAs. - Mahya Morid Ahmadi; Faiq Khalid; Radha Vaidya; Florian Kriebel; Andreas Steininger; Muhammad Shafique 001 (CoRR, 2023)

ISimDL: Importance Sampling-Driven Acceleration of Fault Injection Simulations for Evaluating the Robustness of Deep Learning. - Alessio Colucci; Andreas Steininger; Muhammad Shafique 001 (CoRR, 2023)

The Hidden Behavior of a D-Latch. - Jürgen Maier 002; Andreas Steininger; Robert Najvirt (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

An Autonomous Clock Frequency Supervision Circuit. - Clemens Scharwitzl; Andreas Steininger (DDECS, 2024)

SBanTEM: A Novel Methodology for Sparse Band Tensors as Soft-Error Mitigation in Sparse Convolutional Neural Networks. - Alessio Colucci; Andreas Steininger; Muhammad Shafique 001 (IOLTS, 2024)

EISFINN: On the Role of Efficient Importance Sampling in Fault Injection Campaigns for Neural Network Robustness Analysis. - Alessio Colucci; Andreas Steininger; Muhammad Shafique 001 (IOLTS, 2024)

Muller C-Element for NEMS. - Philipp Lehninger; Axel Jantsch; Andreas Steininger; Elliott Worsey; Victor Marot; Dinesh Pamunuwa (ASYNC, 2025)

Investigating the Effects of Permanent Faults in QDI Circuits: A Formal Perspective. - Raghda El Shehaby; Matthias Függer; Florian Huemer; Andreas Steininger (ASYNC, 2025)