Rapid Evolution of Time-Efficient Packet Classifiers. - Ralf Salomon; Harald Widiger; Andreas Tockhorn (IEEE Congress on Evolutionary Computation, 2006)

Accelerating the Evolution of Evolvable Hardware-based Packet Classifiers. - Harald Widiger; Andreas Tockhorn; Ralf Salomon; Dirk Timmermann (WEAH, 2007)

On the Impact of Caching for High Performance Packet Classifiers. - Harald Widiger; Andreas Tockhorn; Dirk Timmermann (GLOBECOM, 2008)

Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown. - Hagen Sämrow; Claas Cornelius; Frank Sill; Andreas Tockhorn; Dirk Timmermann (SBCCI, 2009)

Modeling temperature distribution in Networks-on-Chip using RC-circuits. - Andreas Tockhorn; Claas Cornelius; Hagen Sämrow; Dirk Timmermann (DDECS, 2010)

Monitoring and Control of Temperature in Networks-on-Chip. - Tim Wegner; Claas Cornelius; Andreas Tockhorn; Dirk Timmermann (MEMICS, 2010)

Functional enhancements of TMR for power efficient and error resilient ASIC designs. - Hagen Sämrow; Claas Cornelius; Philipp Gorski; Jakob Salzmann; Andreas Tockhorn; Dirk Timmermann (DDECS, 2011)

Selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdown. - Hagen Sämrow; Claas Cornelius; Philipp Gorski; Andreas Tockhorn; Dirk Timmermann (DDECS, 2012)

System level modeling of Networks-on-Chip for power estimation and design space exploration. - Martin Gag; Tim Wegner; Philipp Gorski; Andreas Tockhorn; Dirk Timmermann (MBMV, 2013)