Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability. - Andres F. Gomez; Víctor H. Champac (LATS, 2015)

Circuit performance optimization for local intra-die process variations using a gate selection metric. - Víctor H. Champac; Alejandra Nicte-ha Reyes; Andres F. Gomez (VLSI-SoC, 2015)

A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging. - Andres F. Gomez; Víctor H. Champac (VLSI-SoC, 2015)

An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging. - Andres F. Gomez; Leticia B. Poehls; Fabian Vargas 001; Víctor H. Champac (VTS, 2015)

Critical path selection under NBTI/PBTI aging for adaptive frequency tuning. - Andres F. Gomez; Víctor H. Champac (EWDTS, 2016)

A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage. - Freddy Forero; Andres F. Gomez; Víctor H. Champac (LATS, 2016)

Improvement of Negative Bias Temperature Instability Circuit Reliability and Power Consumption Using Dual Supply Voltage. - Freddy Forero; Andres F. Gomez; Víctor H. Champac (J. Low Power Electron., 2016)

Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations. - Andres F. Gomez; Felipe Lavratti; Guilherme Medeiros Machado; M. Sartori; Letícia Maria Veiras Bolzani; Víctor H. Champac; Fabian Vargas 001 (Microelectron. Reliab., 2016)

Early Selection of Critical Paths for Reliable NBTI Aging-Delay Monitoring. - Andres F. Gomez; Víctor H. Champac (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A metric-guided gate-sizing methodology for aging guardband reduction. - Andres F. Gomez; Roberto Gómez 001; Víctor H. Champac (LATS, 2018)

Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection. - Víctor H. Champac; Andres F. Gomez; Freddy Forero; Kaushik Roy 001 (VLSI-SoC (Selected Papers), 2018)

Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations. - Andres F. Gomez; Freddy Forero; Kaushik Roy 001; Víctor H. Champac (VLSI-SoC, 2018)

Selection of Critical Paths for Reliable Frequency Scaling under BTI-Aging Considering Workload Uncertainty and Process Variations Effects. - Andres F. Gomez; Víctor H. Champac (ACM Trans. Design Autom. Electr. Syst., 2018)

An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects. - Andres F. Gomez; Víctor H. Champac (J. Electron. Test., 2019)