An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. - Pascal Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (ISSCC, 2018)

An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop. - Suyoung Bang; Minki Cho; Pascal Meinerzhagen; Andres Malavasi; Muhammad M. Khellah; James W. Tschanz; Vivek De (ESSCIRC, 2019)

Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS. - Pascal Andreas Meinerzhagen; Sandip Kundu; Andres Malavasi; Trang Nguyen; Muhammad M. Khellah; James W. Tschanz; Vivek De (ESSCIRC, 2019)

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{ text{MIN}}$ Optimization. - Pascal Andreas Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (IEEE J. Solid State Circuits, 2019)

25.1 A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS. - Suyoung Bang; Wootaek Lim; Charles Augustine; Andres Malavasi; Muhammad M. Khellah; James W. Tschanz; Vivek De (ISSCC, 2020)

Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation. - Andrés Malavasi-Mora; Renato Rimolo-Donadio (LASCAS, 2020)

Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS. - Jaydeep P. Kulkarni; Andres Malavasi; Charles Augustine; Carlos Tokunaga; Jim Tschanz; Muhammad M. Khellah; Vivek De (VLSI Circuits, 2020)

A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. - Somnath Paul; Turbo Majumder; Charles Augustine; Andres F. Malavasi; S. Usirikayala; Raghavan Kumar; Jisna Kollikunnel; S. Chhabra; Satish Yada; M. L. Barajas; Carlos Ornelas; Dan Lake; et al. (VLSI Circuits, 2020)

Automated Design For Yield Through Defect Tolerance. - Suriyaprakash Natarajan; Andres F. Malavasi; Pascal Andreas Meinerzhagen (VTS, 2020)

An All-Digital, $V_{ mathrm{MAX}}$ -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop. - Suyoung Bang; Minki Cho; Pascal Andreas Meinerzhagen; Andres Malavasi; Muhammad M. Khellah; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2020)

A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses. - Saurabh Kumar 003; Minki Cho; Luke R. Everson; Andres Malavasi; Dan Lake; Carlos Tokunaga; Muhammad M. Khellah; James W. Tschanz; Vivek De; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2021)