Generic Systolic Array for Run-Time Scalable Cores. - Andrés Otero; Yana Esteves Krasteva; Eduardo de la Torre; Teresa Riesgo (ARC, 2010)

A Modular Peripheral to Support Self-Reconfiguration in SoCs. - Andrés Otero; Angel Morales-Cas; Jorge Portilla; Eduardo de la Torre; Teresa Riesgo (DSD, 2010)

Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. - Andrés Otero; Eduardo de la Torre; Teresa Riesgo; Yana Esteves Krasteva (FPL, 2010)

Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors. - Jorge Portilla; Andrés Otero; Eduardo de la Torre; Teresa Riesgo; Oliver Stecklina; Steffen Peter; Peter Langendörfer (Int. J. Distributed Sens. Networks, 2010)

A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems. - Andrés Otero; Rubén Salvador; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (AHS, 2011)

Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (AHS, 2011)

Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs. - Andrés Otero; Eduardo de la Torre; Teresa Riesgo; Teresa Cervero; Sebastián López; Gustavo M. Callicó; Roberto Sarmiento (FPL, 2011)

A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs. - Teresa Cervero; Andrés Otero; Sebastián López; Eduardo de la Torre; Gustavo M. Callicó; Roberto Sarmiento; Teresa Riesgo (ICME, 2011)

Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Lukás Sekanina; Teresa Riesgo (ReConFig, 2011)

On the automatic integration of hardware accelerators into FPGA-based embedded systems. - Christian Pilato; Andrea Cazzaniga; Gianluca Durelli; Andrés Otero; Donatella Sciuto; Marco D. Santambrogio (FPL, 2012)

Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (FPL, 2012)

Automatic generation of identical routing pairs for FPGA implemented DPL logic. - Wei He 015; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (ReConFig, 2012)

Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems. - Andrés Otero; Eduardo de la Torre; Teresa Riesgo (ReConFig, 2012)

Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks. - Juan Valverde; Andrés Otero; Miguel Lopez; Jorge Portilla; Eduardo de la Torre; Teresa Riesgo (Sensors, 2012)

A noise-agnostic self-adaptive image processing application based on evolvable hardware. - Javier Mora 001; Angel Gallego; Andrés Otero; Blanca López; Eduardo de la Torre; Teresa Riesgo (DASIP, 2013)

Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform. - Javier Mora 001; Angel Gallego; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (DASIP, 2013)

A self-adaptive image processing application based on evolvable and scalable hardware. - Angel Gallego; Javier Mora 001; Andrés Otero; Blanca López; Eduardo de la Torre; Teresa Riesgo (FPL, 2013)

A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays. - Angel Gallego; Javier Mora 001; Andrés Otero; Rubén Salvador; Eduardo de la Torre; Teresa Riesgo (IPDPS Workshops, 2013)

A scalable evolvable hardware processing array. - Angel Gallego; Javier Mora 001; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (ReConFig, 2013)

Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (IEEE Trans. Computers, 2013)

A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems. - Juan Valverde; Alfonso Rodríguez 002; Julio Camarero; Andrés Otero; Jorge Portilla; Eduardo de la Torre; Teresa Riesgo (FPL, 2014)

Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic. - Wei He 015; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (Microprocess. Microsystems, 2014)

Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs. - Javier Mora 001; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (ReCoSoC, 2015)

Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis. - Wei He 015; Shivam Bhasin; Andrés Otero; Tarik Graba; Eduardo de la Torre; Jean-Luc Danger (IET Inf. Secur., 2015)

A scalable H.264/AVC deblocking filter architecture. - Teresa Cervero; Andrés Otero; Sebastián López; Eduardo de la Torre; Gustavo M. Callicó; Teresa Riesgo; Roberto Sarmiento (J. Real Time Image Process., 2016)

Dynamic reconfiguration under RTEMS for fault mitigation and functional adaptation in SRAM-based SoPCs for space systems. - Arturo Perez; Leonardo Suriano; Andrés Otero; Eduardo de la Torre (AHS, 2017)

Performance Analysis of SEE Mitigation Techniques on Zynq Ultrascale + Hardened Processing Fabrics. - Arturo Perez; Andrés Otero; Eduardo de la Torre (AHS, 2018)

IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado. - Rafael Zamacola; Alberto García-Martínez; Javier Mora 001; Andrés Otero; Eduardo de la Torre (ReConFig, 2018)

A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images. - Alberto García Ortiz; Alfonso Rodríguez 002; Raúl Guerra; Sebastián López; Andrés Otero; Roberto Sarmiento; Eduardo de la Torre (Remote. Sens., 2018)

FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework. - Alfonso Rodríguez 002; Juan Valverde; Jorge Portilla; Andrés Otero; Teresa Riesgo; Eduardo de la Torre (Sensors, 2018)

Artificial Vision on Edge IoT Devices: A Practical Case for 3D Data Classification. - Cristian Wisultschew; Andrés Otero; Jorge Portilla; Eduardo de la Torre (DCIS, 2019)

Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems. - Rafael Zamacola; Alberto García-Martínez; Javier Mora 001; Andrés Otero; Eduardo de la Torre (FCCM, 2019)

A Fast Prototyping Workflow for Reconfigurable SDR Applications. - Alejandro G. Gener; Juan Valverde; J. Andrés Otero; Philip J. Harris (ReCoSoC, 2019)

Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems. - Alberto García Ortiz; Alfonso Rodríguez 002; Andrés Otero; Eduardo de la Torre (ReCoSoC, 2019)

Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems. - Alberto García Ortiz; Rafael Zamacola; Alfonso Rodríguez 002; Andrés Otero; Eduardo de la Torre (ARC, 2020)

Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation. - Arturo Perez; Alfonso Rodríguez 002; Andrés Otero; David González Arjona; Álvaro Jiménez-Peralo; Miguel Ángel Verdugo; Eduardo de la Torre (IEEE Access, 2020)

Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs. - Leonardo Suriano; Andrés Otero; Alfonso Rodríguez 002; Manuel Sánchez-Renedo; Eduardo de la Torre (IEEE Access, 2020)

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems. - Rafael Zamacola; Andrés Otero; Alberto García-Martínez; Eduardo de la Torre (IEEE Access, 2020)

Run-Time Monitoring and ML-Based Modeling in Reconfigurable Multi-Accelerator Systems. - Juan Encinas; Alfonso Rodríguez 002; Andrés Otero; Eduardo de la Torre (DCIS, 2021)

A Machine-Learning-Based Distributed System for Fault Diagnosis With Scalable Detection Quality in Industrial IoT. - Rodrigo Marino; Cristian Wisultschew; Andrés Otero; José Manuel Lanza-Gutiérrez; Jorge Portilla; Eduardo de la Torre (IEEE Internet Things J., 2021)

Multi-grain reconfigurable and scalable overlays for hardware accelerator composition. - Rafael Zamacola; Andrés Otero; Eduardo de la Torre (J. Syst. Archit., 2021)

A Multi-FPGA Scalable Framework for Deep Reinforcement Learning Through Neuroevolution. - Javier Laserna; Andrés Otero; Eduardo de la Torre (ARC, 2022)

Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays. - Daniel Vázquez; Alfonso Rodríguez 002; Andrés Otero; Eduardo de la Torre (DCIS, 2022)

Just-In-Time Composition of Reconfigurable Overlays (Invited Talk). - Rafael Zamacola; Andrés Otero; Alfonso Rodríguez 002; Eduardo de la Torre (PARMA-DITAM@HiPEAC, 2022)

Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. - Alfonso Rodríguez 002; Andrés Otero; Marco Platzner; Eduardo de la Torre (IEEE Trans. Computers, 2022)

Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning. - Andrés Otero; Guillermo Sanllorente; Eduardo de la Torre; José L. Núñez-Yáñez (ARC, 2023)

A Framework for Fast Prototyping of Photo-realistic Environments with Multiple Pedestrians. - Sara Casao; Andrés Otero; Álvaro Serra-Gómez; Ana C. Murillo; Javier Alonso-Mora; Eduardo Montijano (ICRA, 2023)

Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite. - José L. Núñez-Yáñez; J. Andrés Otero; Eduardo de la Torre (Microprocess. Microsystems, 2023)

Negative emotion recognition based on physiological signals using a CNN-LSTM model. - Junjiao Sun; Jorge Portilla; Andrés Otero (BIBM, 2024)

Open-Source Elastic CGRA Generator. - Daniel Vázquez; Alfonso Rodríguez 002; Andrés Otero (CF (Companion), 2024)

Cloud-Edge Continuum Infrastructure for Reconfigurable Multi-Accelerator Systems. - Iñigo Díez De Ulzurrun; Juan Encinas; Alfonso Rodríguez 002; Andrés Otero (DCIS, 2024)

STRELA: STReaming ELAstic CGRA Accelerator for Embedded Systems. - Daniel Vázquez; José Miranda; Alfonso Rodríguez 002; Andrés Otero; Pasquale Davide Schiavone; David Atienza (CoRR, 2024)

Data-driven modeling of reconfigurable multi-accelerator systems under dynamic workloads. - Juan Encinas; Alfonso Rodríguez 002; Andrés Otero; Eduardo de la Torre (Microprocess. Microsystems, 2024)

A Deep Learning Approach for Fear Recognition on the Edge Based on Two-Dimensional Feature Maps. - Junjiao Sun; Jorge Portilla; Andrés Otero (IEEE J. Biomed. Health Informatics, 2024)

Solving the Cold-Start Problem for the Edge: Clustering and Adaptive Deep Learning for Emotion Detection. - Junjiao Sun; Laura Gutiérrez-Martín; Celia López-Ongil; José Miranda; Jorge Portilla; Andrés Otero (DATE, 2025)

An FPGA-Accelerated Framework for Optimizing Decision Tree Ensembles in Supervised Learning. - Rodrigo Olmos; Andrés Otero (IPDPS (Workshops), 2025)

Leveraging Incremental Machine Learning for Reconfigurable Systems Modeling under Dynamic Workloads. - Juan Encinas; Alfonso Rodríguez 002; Andrés Otero (ACM Trans. Reconfigurable Technol. Syst., 2025)