Real-time pedestrian detection on a xilinx zynq using the HOG algorithm. - Jens Rettkowski; Andrew Boutros; Diana Göhringer (ReConFig, 2015)

Hardware acceleration of novel chaos-based image encryption for IoT applications. - Andrew Boutros; Salma Hesham; Barbara Georgey; Mohamed A. Abd El Ghany (ICM, 2017)

Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis. - Andrew Boutros; Brett Grady; Mustafa Abbas; Paul Chow (ReConFig, 2017)

HW/SW Co-Design of the HOG algorithm on a Xilinx Zynq SoC. - Jens Rettkowski; Andrew Boutros; Diana Göhringer (J. Parallel Distributed Comput., 2017)

Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs. - Andrew Boutros; Sadegh Yazdanshenas; Vaughn Betz (FPL, 2018)

You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference. - Andrew Boutros; Sadegh Yazdanshenas; Vaughn Betz (ACM Trans. Reconfigurable Technol. Syst., 2018)

Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs. - Eriko Nurvitadhi; Dongup Kwon; Ali Jafari; Andrew Boutros; Jaewoong Sim; Phillip Tomson; Huseyin Sumbul; Gregory K. Chen; Phil C. Knag; Raghavan Kumar; Ram Krishnamurthy 001; Sergey Gribok; et al. (FCCM, 2019)

Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs. - Andrew Boutros; Mohamed Eldafrawy; Sadegh Yazdanshenas; Vaughn Betz (FPGA, 2019)

Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI. - Eriko Nurvitadhi; Dongup Kwon; Ali Jafari; Andrew Boutros; Jaewoong Sim; Phillip Tomson; Huseyin Sumbul; Gregory K. Chen; Phil C. Knag; Raghavan Kumar; Ram Krishnamurthy 001; Debbie Marr; et al. (FPGA, 2019)

Scalable Low-Latency Persistent Neural Machine Translation on CPU Server with Multiple FPGAs. - Eriko Nurvitadhi; Mishali Naik; Andrew Boutros; Prerna Budhkar; Ali Jafari; Dongup Kwon; David Sheffield; Abirami Prabhakaran; Karthik Gururaj; Pranavi Appana (FPT, 2019)

Neighbors From Hell: Voltage Attacks Against Deep Learning Accelerators on Multi-Tenant FPGAs. - Andrew Boutros; Mathew Hall; Nicolas Papernot; Vaughn Betz (FPT, 2020)

Beyond Peak Performance: Comparing the Real Performance of AI-Optimized FPGAs and GPUs. - Andrew Boutros; Eriko Nurvitadhi; Rui Ma; Sergey Gribok; Zhipeng Zhao; James C. Hoe; Vaughn Betz; Martin Langhammer (FPT, 2020)

FPGA Logic Block Architectures for Efficient Deep Learning Inference. - Mohamed Eldafrawy; Andrew Boutros; Sadegh Yazdanshenas; Vaughn Betz (ACM Trans. Reconfigurable Technol. Syst., 2020)

Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs. - Xiaowei Wang; Vidushi Goyal; Jiecao Yu; Valeria Bertacco; Andrew Boutros; Eriko Nurvitadhi; Charles Augustine; Ravi R. Iyer 001; Reetuparna Das (FCCM, 2021)

End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression. - Anupreetham Anupreetham; Mohamed Ibrahim; Mathew Hall; Andrew Boutros; Ajay Kuzhively; Abinash Mohanty; Eriko Nurvitadhi; Vaughn Betz; Yu Cao 001; Jae-sun Seo (FPL, 2021)

Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research. - Aman Arora 001; Andrew Boutros; Daniel Rauch; Aishwarya Rajen; Aatman Borda; Seyed Alireza Damghani; Samidh Mehta; Sangram Kate; Pragnesh Patel; Kenneth B. Kent; Vaughn Betz; Lizy K. John (FPL, 2021)

Specializing for Efficiency: Customizing AI Inference Processors on FPGAs. - Andrew Boutros; Eriko Nurvitadhi; Vaughn Betz (ICM, 2021)

RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices. - Andrew Boutros; Eriko Nurvitadhi; Vaughn Betz (FPL, 2022)

Architecture and Application Co-Design for Beyond-FPGA Reconfigurable Acceleration Devices. - Andrew Boutros; Eriko Nurvitadhi; Vaughn Betz (IEEE Access, 2022)

FPGA-Based AI Smart NICs for Scalable Distributed AI Training Systems. - Rui Ma; Evangelos Georganas; Alexander Heinecke; Sergey Gribok; Andrew Boutros; Eriko Nurvitadhi (IEEE Comput. Archit. Lett., 2022)

FPGA-based AI Smart NICs for Scalable Distributed AI Training Systems. - Rui Ma; Evangelos Georganas; Alexander Heinecke; Andrew Boutros; Eriko Nurvitadhi (CoRR, 2022)

Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs. - Zhiqiang Que; Hiroki Nakahara; Eriko Nurvitadhi; Andrew Boutros; Hongxiang Fan; Chenglong Zeng; Jiuxi Meng; Kuen Hung Tsoi; Xinyu Niu; Wayne Luk (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Placement Optimization for NoC-Enhanced FPGAs. - Srivatsan Srinivasan; Andrew Boutros; Fatemehsadat Mahmoudi; Vaughn Betz (FCCM, 2023)

A Whole New World: How to Architect Beyond-FPGA Reconfigurable Acceleration Devices? - Andrew Boutros; Stephen More; Vaughn Betz (FPL, 2023)

Into the Third Dimension: Architecture Exploration Tools for 3D Reconfigurable Acceleration Devices. - Andrew Boutros; Fatemehsadat Mahmoudi; Amin Mohaghegh; Stephen More; Vaughn Betz (ICFPT, 2023)

A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks. - Suyeon Hur; Seongmin Na; Dongup Kwon; Joonsung Kim; Andrew Boutros; Eriko Nurvitadhi; Jangwoo Kim (ACM Trans. Archit. Code Optim., 2023)

Koios 2.0: Open-Source Deep Learning Benchmarks for FPGA Architecture and CAD Research. - Aman Arora 001; Andrew Boutros; Seyed Alireza Damghani; Karan Mathur; Vedant Mohanty; Tanmay Anand; Mohamed A. Elgammal; Kenneth B. Kent; Vaughn Betz; Lizy K. John (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Stay Flexible: A High-Performance FPGA NPU Overlay for Graph Neural Networks. - Taikun Zhang; Andrew Boutros; Sergey Gribok; Kwadwo Boateng; Vaughn Betz (FCCM, 2024)

A Software-Programmable Neural Processing Unit for Graph Neural Network Inference on FPGAs. - Taikun Zhang; Andrew Boutros; Sergey Gribok; Kwadwo Boateng; Vaughn Betz (FPL, 2024)

Field-Programmable Gate Array Architecture for Deep Learning: Survey & Future Directions. - Andrew Boutros; Aman Arora 001; Vaughn Betz (CoRR, 2024)

High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design. - Anupreetham Anupreetham; Mohamed Ibrahim; Mathew Hall; Andrew Boutros; Ajay Kuzhively; Abinash Mohanty; Eriko Nurvitadhi; Vaughn Betz; Yu Cao 001; Jae-Sun Seo (ACM Trans. Reconfigurable Technol. Syst., 2024)

Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage. - Junius Pun; Xilai Dai; Grace Zgheib; Mahesh A. Iyer; Andrew Boutros; Vaughn Betz; Mohamed S. Abdelfattah (CoRR, 2025)