Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU - William J. Bowhill; Shane L. Bell; Bradley J. Benschneider; Andrew J. Black; Sharon M. Britton; Ruben W. Castelino; Dale R. Donchin; John H. Edmondson; Harry R. Fair III; Paul E. Gronowski; Anil K. Jain 003; Patricia L. Kroesen; et al. (Digit. Tech. J., 1995)

A 300-MHz 64-b quad-issue CMOS RISC microprocessor. - Bradley J. Benschneider; Andrew J. Black; William J. Bowhill; Sharon M. Britton; Daniel E. Dever; Dale R. Donchin; Robert J. Dupcak; Richard M. Fromm; Mary K. Gowan; Paul E. Gronowski; Michael Kantrowitz; Marc E. Lamere; et al. (IEEE J. Solid State Circuits, 1995)

A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor. - James Montanaro; Richard T. Witek; Krishna Anne; Andrew J. Black; Elizabeth M. Cooper; Daniel W. Dobberpuhl; Paul M. Donahue; Jim Eno; Gregory W. Hoeppner; David Kruckemyer; Thomas H. Lee; Peter C. M. Lin; et al. (Digit. Tech. J., 1997)

Importance sampling for partially observed temporal epidemic models. - Andrew J. Black (Stat. Comput., 2019)

Neural Likelihood Approximation for Integer Valued Time Series Data. - Luke O'Loughlin; Andrew J. Black; John Maclean (Trans. Mach. Learn. Res., 2024)