Energy-Efficient Hardware Architecture for Variable N-point 1D DCT. - Andrew Kinane; Valentin Muresan; Noel E. O'Connor; Noel Murphy; Seán Marlow (PATMOS, 2004)

FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator. - Andrew Kinane; Alan Casey; Valentin Muresan; Noel E. O'Connor (FPT, 2005)

Optimisation of Constant Matrix Multiplication Operation Hardware Using a Genetic Algorithm. - Andrew Kinane; Valentin Muresan; Noel E. O'Connor (EvoWorkshops, 2006)

Towards Hardware Acceleration of Neuroevolution for Multimedia Processing Applications on Mobile Devices. - Daniel Larkin; Andrew Kinane; Noel E. O'Connor (ICONIP (3), 2006)

Towards an optimised VLSI design algorithm for the constant matrix multiplication problem. - Andrew Kinane; Valentin Muresan; Noel E. O'Connor (ISCAS, 2006)

An Efficient Hardware Architecture for a Neural Network Activation Function Generator. - Daniel Larkin; Andrew Kinane; Valentin Muresan; Noel E. O'Connor (ISNN (2), 2006)

Energy-Efficient Acceleration of MPEG-4 Compression Tools. - Andrew Kinane; Daniel Larkin; Noel E. O'Connor (EURASIP J. Embed. Syst., 2007)

Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse. - Andrew Kinane; Noel E. O'Connor (J. VLSI Signal Process., 2007)