An asynchronous pipelined lattice structure filter. - Uri Cummings; Andrew Lines; Alain J. Martin (ASYNC, 1994)

The Design of an Asynchronous MIPS R3000 Microprocessor. - Alain J. Martin; Andrew Lines; Rajit Manohar; Mika Nyström; Paul I. Pénzes; Robert Southworth; Uri Cummings (ARVLSI, 1997)

Nexus: an asynchronous crossbar interconnect for synchronous system-on-chip designs. - Andrew Lines (Hot Interconnects, 2003)

Asynchronous Interconnect for Synchronous SoC Design. - Andrew Lines (IEEE Micro, 2004)

Slack Matching Asynchronous Designs. - Peter A. Beerel; Nam-Hoon Kim; Andrew Lines; Mike Davies 002 (ASYNC, 2006)

The Vortex: A Superscalar Asynchronous Processor. - Andrew Lines (ASYNC, 2007)

GHz Asynchronous SRAM in 65nm. - Jonathan Dama; Andrew Lines (ASYNC, 2009)

Proteus: An ASIC Flow for GHz Asynchronous Designs. - Peter A. Beerel; Georgios D. Dimou; Andrew Lines (IEEE Des. Test Comput., 2011)

NanoMesh: An Asynchronous Kilo-Core System-on-Chip. - Jonathan Tse; Andrew Lines (ASYNC, 2013)

A 72-Port 10G Ethernet Switch/Router Using Quasi-Delay-Insensitive Asynchronous Design. - Mike Davies 002; Andrew Lines; Jon Dama; Alain Gravel; Robert Southworth; Georgios D. Dimou; Peter A. Beerel (ASYNC, 2014)

Performance-Driven Clustering of Asynchronous Circuits. - Georgios D. Dimou; Peter A. Beerel; Andrew Lines (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Loihi Asynchronous Neuromorphic Research Chip. - Andrew Lines; Prasad Joshi; Ruokun Liu; Steve McCoy; Jonathan Tse; Yi-Hsin Weng; Mike Davies 002 (ASYNC, 2018)

A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes. - Suhwan Kim 002; Vaibhav A. Vaidya; Christopher Schaef; Andrew Lines; Harish Krishnamurthy; Sheldon Weng; Xiaosen Liu; Dileep Kurian; Tanay Karnik; Krishnan Ravichandran; James W. Tschanz; Vivek De (VLSI Circuits, 2018)

Loihi: A Neuromorphic Manycore Processor with On-Chip Learning. - Mike Davies 002; Narayan Srinivasa; Tsung-Han Lin; Gautham N. Chinya; Yongqiang Cao; Sri Harsha Choday; Georgios D. Dimou; Prasad Joshi; Nabil Imam; Shweta Jain 005; Yuyun Liao; Chit-Kwan Lin; et al. (IEEE Micro, 2018)

Asynchronous Serial Infrastructure Using FPIO. - Andrew Lines (ASYNC, 2021)

Clock Generator with Clock Domain Crossing. - Robert Karmazin; Andrew Lines; Prasad Joshi; Benjamin Hill 001 (ASYNC, 2025)

Mount Sisyphus: Energy-Efficient Asynchronous RISC-V Microcontroller in Intel 3 Process. - Andrew Lines; Ruokun Liu (ASYNC, 2025)