An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits. - Greg Leung; Shaodi Wang; Andrew Pan; Puneet Gupta 001; Chi On Chui (IEEE Trans. Very Large Scale Integr. Syst., 2016)

PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices. - Shaodi Wang; Andrew Pan; Chi On Chui; Puneet Gupta 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing. - Shaodi Wang; Saptadeep Pal; Tianmu Li; Andrew Pan; Cecile Grezes; Pedram Khalili Amiri; Kang L. Wang; Puneet Gupta 001 (DATE, 2017)