A Structured Memory Access Architecture - Andrew R. Pleszkun (1982)

Structured Memory Access Architecture. - Andrew R. Pleszkun; Edward S. Davidson (ICPP, 1983)

An algorithm for design rule checking on a multiprocessor. - George E. Bier; Andrew R. Pleszkun (DAC, 1985)

PIPE: A VLSI Decoupled Architecture. - James R. Goodman; Jian-tu Hsieh; Koujuch Liou; Andrew R. Pleszkun; P. B. Schechter; Honesty C. Young (ISCA, 1985)

Implementation of Precise Interrupts in Pipelined Processors. - James E. Smith 001; Andrew R. Pleszkun (ISCA, 1985)

Features of the Structured Memory Access (SMA) Architecture. - Andrew R. Pleszkun; Gurindar S. Sohi; Bassam Z. Kahhaleh; Edward S. Davidson (COMPCON, 1986)

An Architecture for Efficient Lisp List Access. - Andrew R. Pleszkun; Matthew Thazhuthaveetil (ISCA, 1986)

WISQ: A Restartable Architecture Using Queues. - Andrew R. Pleszkun; James R. Goodman; Wei-Chung Hsu; R. T. Joersz; George E. Bier; Philip J. Woest; P. B. Schechter (ISCA, 1987)

The Architecture of Lisp Machines. - Andrew R. Pleszkun; Matthew Thazhuthaveetil (Computer, 1987)

On the Structural Locality of Reference in LISP List Access Streams. - Matthew Thazhuthaveetil; Andrew R. Pleszkun (Inf. Process. Lett., 1987)

The Performance Potential of Multiple Functional Unit Processors. - Andrew R. Pleszkun; Gurindar S. Sohi (ISCA, 1988)

Multiple instruction issue and single-chip processors. - Andrew R. Pleszkun; Gurindar S. Sohi (MICRO, 1988)

Implementing Precise Interrupts in Pipelined Processors. - James E. Smith; Andrew R. Pleszkun (IEEE Trans. Computers, 1988)

Improving Performance of Small On-Chip Instruction Caches. - Matthew K. Farrens; Andrew R. Pleszkun (ISCA, 1989)

An evaluation of functional unit lengths for single-chip processors. - Matthew K. Farrens; Andrew R. Pleszkun (MICRO, 1990)

Strategies for Achieving Improved Processor Throughput. - Matthew K. Farrens; Andrew R. Pleszkun (ISCA, 1991)

Implementation of the PIPE Processor. - Matthew K. Farrens; Andrew R. Pleszkun (Computer, 1991)

MISC: a Multiple Instruction Stream Computer. - Gary S. Tyson; Matthew K. Farrens; Andrew R. Pleszkun (MICRO, 1992)

A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors. - Matthew K. Farrens; Gary S. Tyson; Andrew R. Pleszkun (ISCA, 1994)

Techniques for compressing program address traces. - Andrew R. Pleszkun (MICRO, 1994)

A modified approach to data cache management. - Gary S. Tyson; Matthew K. Farrens; John Matthews; Andrew R. Pleszkun (MICRO, 1995)

Managing data caches using selective cache line replacement. - Gary S. Tyson; Matthew K. Farrens; John Matthews; Andrew R. Pleszkun (Int. J. Parallel Program., 1997)

Confidence Estimation for Speculation Control. - Dirk Grunwald; Artur Klauser; Srilatha Manne; Andrew R. Pleszkun (ISCA, 1998)

Implementation of Precise Interupts in Pipelined Processors. - James E. Smith 001; Andrew R. Pleszkun (25 Years ISCA: Retrospectives and Reprints, 1998)

A Performance Analysis of the iSCSI Protocol. - Stephen Aiken; Dirk Grunwald; Andrew R. Pleszkun; Jesse Willek (IEEE Symposium on Mass Storage Systems, 2003)