Synthesis of array architectures for block matching motion estimation: design exploration using the tool DG2VHDL. - John Bonk; Andrew Stone; Elias S. Manolakos (ICASSP, 1999)

Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis. - Andrew Stone; Elias S. Manolakos (ASAP, 2000)

DG2VHDL: A Tool to Facilitate the High Level Synthesis of Parallel Processing Array Architectures. - Andrew Stone; Elias S. Manolakos (J. VLSI Signal Process., 2000)

Using pre-requirements tracing to investigate requirements based on tactic knowledge. - Andrew Stone; Peter Sawyer (ICSOFT (1), 2006)

Exposing Tacit Knowledge via Pre-Requirements Tracing. - Andrew Stone; Peter Sawyer (RE, 2006)

Identifying tacit knowledge-based requirements. - Andrew Stone; Peter Sawyer (IEE Proc. Softw., 2006)

Profiling and Tracing Stakeholder Needs. - Peter Sawyer; Ricardo Gacitúa; Andrew Stone (Monterey Workshop, 2007)

Automatic Determination of May/Must Set Usage in Data-Flow Analysis. - Andrew Stone; Michelle Strout; Shweta Behere (SCAM, 2008)

May/must analysis and the DFAGen data-flow analysis generator. - Andrew Stone; Michelle Strout; Shweta Behere (Inf. Softw. Technol., 2009)

Abstractions for Defining Semi-Regular Grids Orthogonally from Stencils. - Andrew Stone; Michelle Mills Strout (LCPC, 2012)

Establishing a Miniapp as a programmability proxy. - Andrew Stone; John M. Dennis; Michelle Strout (PPoPP, 2012)

Abstractions to separate concerns in semi-regular grids. - Andrew Stone; Michelle Mills Strout (ICS, 2013)

Loop Chaining: A Programming Abstraction for Balancing Locality and Parallelism. - Christopher D. Krieger; Michelle Mills Strout; Catherine Olschanowsky; Andrew Stone; Stephen M. Guzik; Xinfeng Gao; Carlo Bertolli; Paul H. J. Kelly; Gihan R. Mudalige; Brian van Straalen; Samuel Williams 001 (IPDPS Workshops, 2013)

Local Protection Enforcement in the Path Computation Element Communication Protocol (PCEP). - Andrew Stone; Mustapha Aïssaoui; Samuel Sidor; Siva Sivabalan (RFC, 2023)