Recent Advances in Low Power Asynchronous Circuit Design. - Jia Di; Brent A. Bell; William Bouillon; John Brady; Thao Le 001; Chien-Wei Lo; Liang Men; Spencer Nelson; Francis Sabado; Andrew Suchanek (J. Low Power Electron., 2017)

A 0.2-2 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving 2.55-448.6 ns Programmable Delay Range and 330 ns/mm2 Area Efficiency. - Travis Forbes; Benjamin Magstadt; Jesse Moody; Justine Saugen; Andrew Suchanek; Spencer Nelson (IEEE J. Solid State Circuits, 2023)

Fail-Safe Logic Design Strategies Within Modern FPGA Architectures. - Priya A. Bhakta; Jim Plusquellic; Andrew Suchanek; Tom J. Mannos (IEEE Access, 2025)