Roofline: an insightful visual performance model for multicore architectures. - Samuel Williams 001; Andrew Waterman; David A. Patterson 001 (Commun. ACM, 2009)

RAMP gold: an FPGA-based architecture simulator for multiprocessors. - Zhangxi Tan; Andrew Waterman; Rimas Avizienis; Yunsup Lee; Henry Cook; David A. Patterson 001; Krste Asanovic (DAC, 2010)

A case for FAME: FPGA architecture model execution. - Zhangxi Tan; Andrew Waterman; Henry Cook; Sarah Bird; Krste Asanovic; David A. Patterson 001 (ISCA, 2010)

Chisel: constructing hardware in a Scala embedded language. - Jonathan Bachrach; Huy Vo; Brian C. Richards; Yunsup Lee; Andrew Waterman; Rimas Avizienis; John Wawrzynek; Krste Asanovic (DAC, 2012)

Measuring the gap between programmable and fixed-function accelerators: A case study on speech recognition. - Yunsup Lee; David Sheffield; Andrew Waterman; Michael J. Anderson; Kurt Keutzer; Krste Asanovic (Hot Chips Symposium, 2013)

The RISC-V instruction set. - Andrew Waterman; Yunsup Lee; Rimas Avizienis; Henry Cook; David A. Patterson 001; Krste Asanovic (Hot Chips Symposium, 2013)

A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators. - Yunsup Lee; Andrew Waterman; Rimas Avizienis; Henry Cook; Chen Sun 003; Vladimir Stojanovic; Krste Asanovic (ESSCIRC, 2014)

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. - Yunsup Lee; Brian Zimmer; Andrew Waterman; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Henry Cook; Rimas Avizienis; et al. (Hot Chips Symposium, 2015)

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (VLSIC, 2015)

Single-chip microprocessor that communicates directly using light. - Chen Sun 003; Mark T. Wade; Yunsup Lee; Jason S. Orcutt; Luca Alloatti; Michael Georgas; Andrew Waterman; Jeffrey M. Shainline; Rimas Avizienis; Sen Lin 002; Benjamin Moss; Rajesh Kumar; et al. (Nat., 2015)

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Steven Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (IEEE J. Solid State Circuits, 2016)

An Agile Approach to Building RISC-V Microprocessors. - Yunsup Lee; Andrew Waterman; Henry Cook; Brian Zimmer; Ben Keller; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Rimas Avizienis; et al. (IEEE Micro, 2016)

Design of the RISC-V Instruction Set Architecture. - Andrew Waterman (2016)

Microprocessor chip with photonic I/O. - Chen Sun 003; Mark T. Wade; Yunsup Lee; Jason S. Orcutt; Luca Alloatti; Michael S. Georgas; Andrew S. Waterman; Jeffrey M. Shainline; Rimas R. Avizienis; Sen Lin 002; Benjamin R. Moss; Rajesh Kumar; et al. (OFC, 2017)

FASED: FPGA-Accelerated Simulation and Evaluation of DRAM. - David Biancolin; Sagar Karandikar; Donggyu Kim; Jack Koenig; Andrew Waterman; Jonathan Bachrach; Krste Asanovic (FPGA, 2019)

Managing Chip Design Complexity in the Domain-Specific SoC Era. - Yunsup Lee; Andrew Waterman (VLSI Circuits, 2020)