Comments on "Procedures for Eliminating Static and Dynamic-Hazards in Test Generation". - Andrzej Hlawiczka (IEEE Trans. Computers, 1978)

Compression of multiple-valued data serial streams by means of parallel LFSR signature analyzer. - Andrzej Hlawiczka (Fehlertolerierende Rechensysteme, 1984)

Compression of Three-State Data Serial Streams by Means of a Parallel LFSR Signature Analyzer. - Andrzej Hlawiczka (IEEE Trans. Computers, 1986)

Universal Test Controller Chip for Board Self Test. - Andrzej Hlawiczka; Dariusz Badura (Fehlertolerierende Rechensysteme, 1987)

Signature Analysis Testing with Bottom-Top Exclusive Or Type MISR. - Andrzej Hlawiczka (Fehlertolerierende Rechensysteme, 1989)

Parallel Signature Analyzers Using Hybrid Design of Their Linear Feedbacks. - Andrzej Hlawiczka (IEEE Trans. Computers, 1992)

Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera Structures. - Andrzej Hlawiczka; Jacek Binda (FPL, 1994)

Low Cost Bist for Edac Circuits. - Dariusz Badura; Andrzej Hlawiczka (Asian Test Symposium, 1997)

A linear code-preserving signature analyzer COPMISR. - Andrzej Hlawiczka; Michael Gössel; Egor S. Sogomonyan (VTS, 1997)

A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits. - Tomasz Garbolino; Andrzej Hlawiczka (EDCC, 1999)

Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata. - Andrzej Hlawiczka; Michal Kopec (Asian Test Symposium, 2000)

Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path. - Tomasz Garbolino; Andrzej Hlawiczka; Adam Kristof (ETW, 2000)

Dependable testing of compactor MISR: an imperceptible problem? - Andrzej Hlawiczka; Michal Kopec (ETW, 2002)

Efficient test pattern generators based on specific cellular automata structures. - Tomasz Garbolino; Andrzej Hlawiczka (Microelectron. Reliab., 2002)

Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor. - Ondrej Novák; Zdenek Plíva; Jiri Nosek; Andrzej Hlawiczka; Tomasz Garbolino; Krzysztof Gucwa (J. Electron. Test., 2004)

Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor. - Tomasz Garbolino; Michal Kopec; Krzysztof Gucwa; Andrzej Hlawiczka (DDECS, 2006)

Test-per-Clock Detection, Localization and Identification of Interconnect Faults. - Michal Kopec; Tomasz Garbolino; Krzysztof Gucwa; Andrzej Hlawiczka (ETS, 2006)

Avoiding Crosstalk Influence on Interconnect Delay Fault Testing. - Tomasz Garbolino; Krzysztof Gucwa; Michal Kopec; Andrzej Hlawiczka (DDECS, 2007)

Test Pattern Generator for Delay Faults. - Tomasz Rudnicki; Andrzej Hlawiczka (DDECS, 2007)

Interconnect Faults Identification and Localization Using Modified Ring LFSRs. - Andrzej Hlawiczka; Krzysztof Gucwa; Tomasz Garbolino; Michal Kopec (DDECS, 2008)

Effective BIST for crosstalk faults in interconnects. - Tomasz Rudnicki; Tomasz Garbolino; Krzysztof Gucwa; Andrzej Hlawiczka (DDECS, 2009)

How to reduce size of a signature-based diagnostic dictionary used for testing of connections. - Tomasz Garbolino; Krzysztof Gucwa; Andrzej Hlawiczka (DDECS, 2010)

Reduced-size signature-based diagnostic dictionary for interconnection testing. - Tomasz Garbolino; Krzysztof Gucwa; Andrzej Hlawiczka (PDeS, 2010)