Statistical Simulation of the IC Manufacturing Process. - Wojciech Maly; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1982)

FABRICS II: A Statistically Based IC Fabrication Process Simulator. - Sani R. Nassif; Andrzej J. Strojwas; Stephen W. Director (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984)

PROD: A VLSI Fault Diagnosis System. - Peter Odryna; Andrzej J. Strojwas (IEEE Des. Test, 1985)

A Pattern Recognition Based Method for IC Failure Analysis. - Andrzej J. Strojwas; Stephen W. Director (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985)

Yield of VLSI circuits: myths vs. reality (panel). - Andrzej J. Strojwas; Clark Beck; Dennis Buss; Tülin Erdim Mangir; Charles H. Stapper (DAC, 1986)

The CMU-CAM System. - Andrzej J. Strojwas (IEEE Des. Test, 1986)

VLSI Yield Prediction and Estimation: A Unified Framework. - Wojciech Maly; Andrzej J. Strojwas; Stephen W. Director (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986)

A Methodology for Worst-Case Analysis of Integrated Circuits. - Sani R. Nassif; Andrzej J. Strojwas; Stephen W. Director (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986)

A Statistical Design Rule Developer. - Rahul Razdan; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986)

A New Approach to Hierarchical and Statistical Timing Simulations. - Jacques Benkoski; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

A Methodology for Optimal Test Structure Design for Statistical Process Characterization and Diagnosis. - Ihao Chen; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Realistic Yield Simulation for VLSIC Structural Failures. - Ihao Chen; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

The process engineer's workbench. - Andrzej J. Strojwas; Stephen W. Director (IEEE J. Solid State Circuits, 1988)

Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator. - Jacques Benkoski; Andrzej J. Strojwas (DAC, 1989)

Design for Manufacturability and Yield. - Andrzej J. Strojwas (DAC, 1989)

Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator. - Jacques Benkoski; Andrzej J. Strojwas (ITC, 1989)

Statistical control of VLSI fabrication processes. - Purnendu K. Mozumder; Andrzej J. Strojwas (Proc. IEEE, 1990)

The Role of Timing Verification in Layout Synthesis. - Jacques Benkoski; Andrzej J. Strojwas (DAC, 1991)

Utilizing Logic Information in Multi-Level Timing Simulation. - Marko P. Chew; Andrzej J. Strojwas (DAC, 1991)

A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator. - D. M. H. Walker; Chris S. Kellen; Andrzej J. Strojwas (DAC, 1991)

An efficient algorithm for parametric fault simulation of monolithic IC's. - Andrzej J. Strojwas; Stephen W. Director (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Numerical integral method for diffusion modeling. - Xiaowei Tian; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

A methodology for improved circuit simulation efficiency via topology-based variable accuracy device modeling. - Kimon W. Michaels; Andrzej J. Strojwas (ICCAD, 1992)

Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures. - Shigetaka Kumashiro; Ronald A. Rohrer; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

The CDB/HCDB semiconductor wafer representation server. - D. M. H. Walker; Chris S. Kellen; David M. Svoboda; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

MONSTR: A Complete Thermal Simulator of Electronic Systems. - Vladimir A. Koval; Igor W. Farmaga; Andrzej J. Strojwas; Stephen W. Director (DAC, 1994)

Variable Accuracy Device Modeling for Event-Driven Circuit Simulation. - Kimon W. Michaels; Andrzej J. Strojwas (EDAC-ETC-EUROASIC, 1994)

Towards Incorporating Device Parameter Variations in Timing Analysis. - Mukund Sivaraman; Andrzej J. Strojwas (EDAC-ETC-EUROASIC, 1994)

Stochastic Interpolation Model Scheme for Statistical Circuit Design. - Jin-Qin Lu; Kimihiro Ogawa; Takehiko Adachi; Andrzej J. Strojwas (ISCAS, 1994)

Test Vector Generation for Parametric Path Delay Faults. - Mukund Sivaraman; Andrzej J. Strojwas (ITC, 1995)

Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults. - Mukund Sivaraman; Andrzej J. Strojwas (ICCAD, 1996)

Manufacturability of low power CMOS technology solutions. - Andrzej J. Strojwas; Michele Quarantelli; J. Borel; Carlo Guardiani; Germano Nicollini; G. Crisenza; Bruno Franzini; J. Wiart (ISLPED, 1996)

Diagnosis of parametric path delay faults. - Mukund Sivaraman; Andrzej J. Strojwas (VLSI Design, 1996)

A diagnosability metric for parametric path delay faults. - Mukund Sivaraman; Andrzej J. Strojwas (VTS, 1996)

Timing analysis based on primitive path delay fault identification. - Mukund Sivaraman; Andrzej J. Strojwas (ICCAD, 1997)

Primitive Path Delay Fault Identification. - Mukund Sivaraman; Andrzej J. Strojwas (VLSI Design, 1997)

ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models. - Ying Liu; Lawrence T. Pileggi; Andrzej J. Strojwas (DAC, 1998)

A pattern matching algorithm for verification and analysis of very large IC layouts. - Mariusz Niewczas; Wojciech Maly; Andrzej J. Strojwas (ISPD, 1998)

Model Order-Reduction of RC(L) Interconnect Including Variational Analysis. - Ying Liu; Lawrence T. Pileggi; Andrzej J. Strojwas (DAC, 1999)

A New Methodology for Concurrent Technology Development and Cell Library Optimization. - Marko P. Chew; Sharad Saxena; Thomas F. Cobourn; Purnendu K. Mozumder; Andrzej J. Strojwas (VLSI Design, 1999)

An algorithm for determining repetitive patterns in very large IC layouts. - Mariusz Niewczas; Wojciech Maly; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Design for manufacturability: a path from system level to high yielding chips: embedded tutorial. - Andrzej J. Strojwas (ASP-DAC, 2000)

Impact of interconnect variations on the clock skew of a gigahertz microprocessor. - Ying Liu; Sani R. Nassif; Lawrence T. Pileggi; Andrzej J. Strojwas (DAC, 2000)

When bad things happen to good chips (panel session). - N. S. Nagaraj; Andrzej J. Strojwas; Sani R. Nassif; Ray Hokinson; Tak Young; Wonjae L. Kang; David Overhauser; Sung-Mo Kang (DAC, 2000)

Design-Manufacturing Interface for 0.13 Micron and Below. - Andrzej J. Strojwas (ICCAD, 2000)

Design-Manufacturing Interface in the Deep Submicron: Is Technology Independent Design Dead? - Carlo Guardiani; Andrzej J. Strojwas (ISQED, 2000)

Perspectives on technology and technology-driven CAD. - Robert W. Dutton; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Primitive path delay faults: identification and their use in timinganalysis. - Mukund Sivaraman; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Path delay fault diagnosis and coverage-a metric and an estimationtechnique. - Mukund Sivaraman; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Congestion-Aware Logic Synthesis. - Davide Pandini; Lawrence T. Pileggi; Andrzej J. Strojwas (DATE, 2002)

Understanding and addressing the impact of wiring congestion during technology mapping. - Davide Pandini; Lawrence T. Pileggi; Andrzej J. Strojwas (ISPD, 2002)

Exploring regular fabrics to optimize the performance-cost trade-off. - Lawrence T. Pileggi; Herman Schmit; Andrzej J. Strojwas; Padmini Gopalakrishnan; V. Kheterpal; Aneesh Koorapaty; Chetan Patel; Vyacheslav Rovner; Kim Yaw Tong (DAC, 2003)

Bounding the efforts on congestion optimization for physical synthesis. - Davide Pandini; Lawrence T. Pileggi; Andrzej J. Strojwas (ACM Great Lakes Symposium on VLSI, 2003)

Global and local congestion optimization in technology mapping. - Davide Pandini; Lawrence T. Pileggi; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Routing architecture exploration for regular fabrics. - V. Kheterpal; Andrzej J. Strojwas; Lawrence T. Pileggi (DAC, 2004)

When IC yield missed the target, who is at fault? - Andreas J. Strojwas; Michael Campbell; Vassilios Gerousis; Jim Hogan; John Kibarian; Marc Levitt; Walter Ng; Dipu Pramanik; Mark Templeton (DAC, 2004)

Design methodology for IC manufacturability based on regular logic-bricks. - V. Kheterpal; Vyacheslav Rovner; T. G. Hersan; D. Motiani; Y. Takegawa; Andrzej J. Strojwas; Lawrence T. Pileggi (DAC, 2005)

Correlation-aware statistical timing analysis with non-gaussian delay distributions. - Yaping Zhan; Andrzej J. Strojwas; Xin Li 001; Lawrence T. Pileggi; David Newmark; Mahesh Sharma (DAC, 2005)

Projection-based performance modeling for inter/intra-die variations. - Xin Li 001; Jiayong Le; Lawrence T. Pileggi; Andrzej J. Strojwas (ICCAD, 2005)

Statistical critical path analysis considering correlations. - Yaping Zhan; Andrzej J. Strojwas; Mahesh Sharma; David Newmark (ICCAD, 2005)

Tutorial on DFM for physical design. - Andrzej J. Strojwas (ISPD, 2005)

Guest Editors' Introduction: DFM Drives Changes in Design Flow. - Juan Antonio Carballo; Yervant Zorian; Raul Camposano; Andrzej J. Strojwas; John Kibarian; Dennis Wassung; Alex Alexanian; Steve Wigley; Neil Kelly (IEEE Des. Test Comput., 2005)

DFM/DFY: should you trust the surgeon or the family doctor? - Marco Casale-Rossi; Andrzej J. Strojwas; Robert C. Aitken; Antun Domic; Carlo Guardiani; Philippe Magarshack; Douglas Pattullo; Joseph Sawicki (DATE, 2007)

Creating an affordable 22nm node using design-lithography co-optimization. - Andrzej J. Strojwas; Tejas Jhaveri; Vyacheslav Rovner; Lawrence T. Pileggi (DAC, 2009)

Who solves the variability problem? - Nagaraj Ns; Juan C. Rey; Jamil Kawa; Robert C. Aitken; Christian Lütkemeyer; Vijay Pitchumani; Andrzej J. Strojwas; Steve Trimberger (DAC, 2010)

Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings. - Tejas Jhaveri; Vyacheslav Rovner; Lars Liebmann; Larry T. Pileggi; Andrzej J. Strojwas; Jason Hibbeler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Cost effective scaling to 22nm and below technology nodes. - Andrzej J. Strojwas (DDECS, 2011)

Automatic clustering of wafer spatial signatures. - Wangyang Zhang; Xin Li 001; Sharad Saxena; Andrzej J. Strojwas; Rob A. Rutenbar (DAC, 2013)

Efficient Spatial Pattern Analysis for Variation Decomposition Via Robust Sparse Regression. - Wangyang Zhang; Karthik Balakrishnan; Xin Li 001; Duane S. Boning; Sharad Saxena; Andrzej J. Strojwas; Rob A. Rutenbar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Sub-20 nm design technology co-optimization for standard cell logic. - Kaushik Vaidyanathan; Lars Liebmann; Andrzej J. Strojwas; Larry T. Pileggi (ICCAD, 2014)

Keynote address: Challenges and opportunities in electrical characterization and test for 14nm and below. - Andrzej J. Strojwas; Jacob A. Abraham; Hong Hao; Max M. Shulaker (VTS, 2016)

Yield and Reliability Challenges at 7nm and Below. - Andrzej J. Strojwas; Kelvin Doong; Dennis J. Ciplickas (MIXDES, 2019)

In-Product BTI Aging Sensor for Reliability Screening and Early Detection of Material at Risk. - Tomasz Brozek; Alberto A. P. Cattaneo; Larg Weiland; Michele Quarantelli; Alberto Coccoli; Sharad Saxena; Christopher Hess; Andrzej J. Strojwas (IRPS, 2023)