Fuzzy Automata as Adaptive Algorithms for Telephone Traffic Routing. - Andrzej Krasniewski (ICC (1), 1984)

Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications. - Andrzej Krasniewski; Alexander Albicki (DAC, 1985)

Automatic Design of Exhaustively Self-Testing Chips with Bilbo Modules. - Andrzej Krasniewski; Alexander Albicki (ITC, 1985)

Circular Self-Test Path: A Low-Cost BIST Technique. - Andrzej Krasniewski; Slawomir Pilarski (DAC, 1987)

Circular self-test path: a low-cost BIST technique for VLSI circuits. - Andrzej Krasniewski; Slawomir Pilarski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Design for verification testability. - Andrzej Krasniewski (EURO-DAC, 1990)

Logic Synthesis for Efficient Pseudoexhaustive Testability. - Andrzej Krasniewski (DAC, 1991)

Random Testability of Redundant Circuits. - Andrzej Krasniewski; Alexander Albicki (ICCD, 1991)

Can Redundancy Enhance Testability? - Andrzej Krasniewski (ITC, 1991)

Design of Robust-Path-Delay-Fault-Testable Combinational Circuits by Boolean Space Expansion. - Xiaodong Xie; Alexander Albicki; Andrzej Krasniewski (ICCD, 1992)

High Quality Testing of Embedded RAMs Using Circular Self-Test Path. - Andrzej Krasniewski; Slawomir Pilarski (ITC, 1992)

Estimating testing effectiveness of the circular self-test path technique. - Slawomir Pilarski; Andrzej Krasniewski; Tiko Kameda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Coverage of Delay Faults: When 13% and 99% Mean the Same. - Andrzej Krasniewski; Leszek B. Wronski (EDCC, 1994)

Tests for path delay faults vs. tests for gate delay faults: how different they are. - Andrzej Krasniewski; Leszek B. Wronski (EURO-DAC, 1994)

Design of Dependable Hardware: What BIST is most Efficient? - Andrzej Krasniewski (EDCC, 1996)

Application-Dependent Testing of FPGA Delay Faults. - Andrzej Krasniewski (EUROMICRO, 1999)

Self-Testing of S-Compatible Test Units in User-Programmed FPGAs. - Pawel Tomaszewicz; Andrzej Krasniewski (EUROMICRO, 1999)

Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs. - Andrzej Krasniewski (FPL, 2000)

Self-Testing of FPGA Delay Faults in the System Environment. - Andrzej Krasniewski (IOLTW, 2000)

Evaluation of Delay Fault Testability of LUT Functions for Improved Efficiency of FPGA Testing. - Andrzej Krasniewski (DSD, 2001)

Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing. - Andrzej Krasniewski (IOLTW, 2001)

On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs. - Andrzej Krasniewski (FPL, 2002)

Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs. - Andrzej Krasniewski (FPL, 2002)

Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices. - Andrzej Krasniewski (FPL, 2003)

Evaluation of the Quality of Testing Path Delay Faults under Restricted Input Assumption. - Andrzej Krasniewski (IOLTS, 2003)

Evaluation of delay fault testability of LUTs for the enhancement of application-dependent testing of FPGAs. - Andrzej Krasniewski (J. Syst. Archit., 2003)

Concurrent Error Detection in Sequential Circuits Implemented Using Embedded Memory of LUT-Based FPGAs. - Andrzej Krasniewski (DFT, 2004)

Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory. - Andrzej Krasniewski (FPL, 2004)

Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory Blocks. - Andrzej Krasniewski (IOLTS, 2004)

A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory. - Andrzej Krasniewski (IOLTS, 2005)

Low-Cost Concurrent Error Detection for FSMs Implemented Using Embedded Memory Blocks of FPGAs. - Andrzej Krasniewski (DDECS, 2006)

Concurrent Error Detection for FSMs Designed for Implementation with Embedded Memory Blocks of FPGAs. - Andrzej Krasniewski (DSD, 2007)

Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs. - Andrzej Krasniewski (DDECS, 2008)

Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAs. - Andrzej Krasniewski (DSD, 2008)

Concurrent error detection for finite state machines implemented with embedded memory blocks of SRAM-based FPGAs. - Andrzej Krasniewski (Microprocess. Microsystems, 2008)

Trading-Off Error Detection Efficiency with Implementation Cost for Sequential Circuits Implemented with FPGAs. - Grzegorz Borowik; Andrzej Krasniewski (EUROCAST (2), 2011)

A Tool for Trading-Off On-Line Error Detection Efficiency with Implementation Cost for Sequential Logic Implemented in FPGAs. - Grzegorz Borowik; Andrzej Krasniewski (ICSEng, 2011)

Evaluation of susceptibility of FPGA-based circuits to fault injection attacks based on clock glitching. - Jakub Korczyc; Andrzej Krasniewski (DDECS, 2012)

Rule Induction Based on Logic Synthesis Methods. - Grzegorz Borowik; Andrzej Krasniewski; Tadeusz Luba (ICSEng, 2014)