Evaluation of parasitic capacitances for interconnection buses crossing in different layers. - Adam Jarosz; Andrzej Pfitzner (Microelectron. Reliab., 2005)

Is there always performance overhead for regular fabric? - Yi-Wei Lin; Malgorzata Marek-Sadowska; Wojciech Maly; Andrzej Pfitzner; Dominik Kasprowicz (ICCD, 2008)

Adder Circuits with Transistors using Independently Controlled Gates. - Marcus Weis; Andrzej Pfitzner; Dominik Kasprowicz; Rainer Emling; Wojciech Maly; Doris Schmitt-Landsiedel (ISCAS, 2009)

Vertical Slit Transistor based Integrated Circuits (VeSTICs). - Andrzej Pfitzner (DDECS, 2012)

Improved simple DC model of Vertical-Slit Field-Effect Transistor (VeSFET). - Andrzej Pfitzner (MIXDES, 2014)

Usefulness of VeSTIC devices for low-noise and radiation hard 3D integrated circuits. - Michal Staniewski; Andrzej Pfitzner (MIXDES, 2014)

Compact DC model of a JVeSFET transistor with reduced number of empirical parameters. - Michal Staniewski; Andrzej Pfitzner (MIXDES, 2015)

Contribution to scaling of Vertical-Slit Field-Effect Transistor (VeSFET). - Andrzej Pfitzner; Beata Kowalska (MIXDES, 2016)

Feasibility Studies of EEPROM Memory Implementations in VeSTIC Technology. - Bartosz Dec; Andrzej Pfitzner (MIXDES, 2018)

Optimization of the VeSFET Structure Dedicated to Basic Logic Cells in VeSTIC Technology. - Mikolaj Palgan; Andrzej Pfitzner (MIXDES, 2018)

Study of Storage Capacity of Charge Trap EAROM NAND Memory Designed for Integration with VeSTIC Technology. - Bartosz Dec; Andrzej Pfitzner (MIXDES, 2024)