A Power Optimized Display Memory Organization for Handheld User Terminal. - Lieven Hollevoet; Andy Dewilde; Kristof Denolf; Francky Catthoor; Filip Louagie (DATE, 2004)

Real Time Prototyping of Broadband Wireless LAN Systems. - Maryse Wouters; Peter Van Wesemael; Roeland Vandebriel; Andy Dewilde; Michael Libois (IEEE International Workshop on Rapid System Prototyping, 2004)

A flexible platform architecture for Gbps wireless communication. - Jeroen Declerck; Prabhat Avasare; Miguel Glassee; Amir Amin; Erik Umans; Andy Dewilde; Praveen Raghavan; Martin Palkovic (ISSoC, 2012)

DART - a High Level Software-Defined Radio Platform Model for Developing the Run-Time Controller. - Martin Palkovic; Jeroen Declerck; Prabhat Avasare; Miguel Glassee; Andy Dewilde; Praveen Raghavan; Antoine Dejonghe; Liesbet Van der Perre (J. Signal Process. Syst., 2012)

An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS. - Meng Li 012; Jan-Willem Weijers; Veerle Derudder; Ilse Vos; Maxim Rykunov; Steven Dupont; Peter Debacker; Andy Dewilde; Yanxiang Huang; Liesbet Van der Perre; Wim Van Thillo (A-SSCC, 2015)

Parallelized correlator bank for a 1 GHz bandwidth phase modulated CW radar in the 79GHz band. - Yuzhu Gai; Andy Dewilde; Ubaid Ahmad; André Bourdoux; Sofie Pollin (SCVT, 2015)

A 79GHz 2×2 MIMO PMCW radar SoC in 28nm CMOS. - Davide Guermandi; Qixian Shi; Andy Dewilde; Veerle Derudder; Ubaid Ahmad; Annachiara Spagnolo; André Bourdoux; Piet Wambacq; Wim Van Thillo (A-SSCC, 2016)

A 79-GHz 2 × 2 MIMO PMCW Radar SoC in 28-nm CMOS. - Davide Guermandi; Qixian Shi; Andy Dewilde; Veerle Derudder; Ubaid Ahmad; Annachiara Spagnolo; Ilja Ocket; André Bourdoux; Piet Wambacq; Jan Craninckx; Wim Van Thillo (IEEE J. Solid State Circuits, 2017)

A 100 Gbps LDPC Decoder for the IEEE 802.11ay Standard. - Meng Li 012; Veerle Derudder; Claude Desset; Andy Dewilde; André Bourdoux; Yanxiang Huang (ISTC, 2018)