Putting Data Value Predictors to Work in Fine-Grain Parallel Processors. - Aneesh Aggarwal; Manoj Franklin (HiPC, 2001)

Evaluating the impact of memory system performance on software prefetching and locality optimizations. - Abdel-Hameed A. Badawy; Aneesh Aggarwal; Donald Yeung; Chau-Wen Tseng (ICS, 2001)

An empirical study of the scalability aspects of instruction distribution algorithms for clustered processors. - Aneesh Aggarwal; Manoj Franklin (ISPASS, 2001)

Related Field Analysis. - Aneesh Aggarwal; Keith H. Randall (PLDI, 2001)

Hierarchical Interconnects for On-Chip Clustering. - Aneesh Aggarwal; Manoj Franklin (IPDPS, 2002)

Software caching vs. prefetching. - Aneesh Aggarwal (MSP/ISMM, 2002)

Energy Efficient Asymmetrically Ported Register Files. - Aneesh Aggarwal; Manoj Franklin (ICCD, 2003)

Single FU Bypass Networks for High Clock Rate Superscalar Processors. - Aneesh Aggarwal (HiPC, 2004)

Defining Wakeup Width for Efficient Dynamic Scheduling. - Aneesh Aggarwal; Manoj Franklin; Oguz Ergin (ICCD, 2004)

Bit-Sliced Datapath for Energy-Efficient High Performance Microprocessors. - Sumeet Kumar; Prateek Pujara; Aneesh Aggarwal (PACS, 2004)

The Efficacy of Software Prefetching and Locality Optimizations on Future Memory Systems. - Abdel-Hameed A. Badawy; Aneesh Aggarwal; Donald Yeung; Chau-Wen Tseng (J. Instr. Level Parallelism, 2004)

Restrictive Compression Techniques to Increase Level 1 Cache Capacity. - Prateek Pujara; Aneesh Aggarwal (ICCD, 2005)

Reducing latencies of pipelined cache accesses through set prediction. - Aneesh Aggarwal (ICS, 2005)

Instruction Replication for Reducing Delays Due to Inter-PE Communication Latency. - Aneesh Aggarwal; Manoj Franklin (IEEE Trans. Computers, 2005)

Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors. - Aneesh Aggarwal; Manoj Franklin (IEEE Trans. Parallel Distributed Syst., 2005)

Self-checking instructions: reducing instruction redundancy for concurrent error detection. - Sumeet Kumar; Aneesh Aggarwal (PACT, 2006)

Trade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors. - Joseph J. Sharkey; Nayef Abu-Ghazeleh; Dmitry V. Ponomarev; Kanad Ghose; Aneesh Aggarwal (HiPC, 2006)

Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors. - Sumeet Kumar; Aneesh Aggarwal (HPCA, 2006)

Increasing the cache efficiency by eliminating noise. - Prateek Pujara; Aneesh Aggarwal (HPCA, 2006)

Address-Value Decoupling for Early Register Deallocation. - Deniz Balkan; Joseph J. Sharkey; Dmitry Ponomarev 001; Aneesh Aggarwal (ICPP, 2006)

McGrid: framework for optimizing grid middleware on multi-core processors. - Rajdeep Bhowmik; Chaitali Gupta; Madhusudhan Govindaraju; Aneesh Aggarwal (SOCP@HPDC, 2007)

Increasing cache capacity through word filtering. - Prateek Pujara; Aneesh Aggarwal (ICS, 2007)

Efficient XML-Based Grid Middleware Design for Multi-Core Processors. - Rajdeep Bhowmik; Chaitali Gupta; Madhusudhan Govindaraju; Aneesh Aggarwal (ICWS, 2007)

Introduction to the special issue on the 2006 reconfigurable and adaptive architecture workshop. - Aneesh Aggarwal; Pradip Bose; Mohamed Zahran (SIGARCH Comput. Archit. News, 2007)

Scalable Multi-cores with Improved Per-core Performance Using Off-the-critical Path Reconfigurable Hardware. - Tameesh Suri; Aneesh Aggarwal (HiPC, 2008)

Speculative instruction validation for performance-reliability trade-off. - Sumeet Kumar; Aneesh Aggarwal (HPCA, 2008)

Optimizing XML processing for grid applications using an emulation framework. - Rajdeep Bhowmik; Chaitali Gupta; Madhusudhan Govindaraju; Aneesh Aggarwal (IPDPS, 2008)

Cache Noise Prediction. - Prateek Pujara; Aneesh Aggarwal (IEEE Trans. Computers, 2008)

Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration. - Tameesh Suri; Aneesh Aggarwal (Conf. Computing Frontiers, 2009)

Architectural support for low overhead detection of memory violations. - Saugata Ghose; Latoya Gilgeous; Polina Dudnik; Aneesh Aggarwal; Corey Waxman (DATE, 2009)

Exploring the Limits of Port Reduction in Centralized Register Files. - Sandeep Sirsi; Aneesh Aggarwal (VLSI Design, 2009)

Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration. - Tameesh Suri; Aneesh Aggarwal (VLSI Design, 2009)

Complexity Effective Bypass Networks. - Aneesh Aggarwal (Trans. High Perform. Embed. Archit. Compil., 2009)

Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration. - Tameesh Suri; Aneesh Aggarwal (Int. J. Parallel Program., 2010)

Adaptive and Scalable Predictive Page Policies for High Core-Count Server CPUs. - Tameesh Suri; Aneesh Aggarwal (ARCS, 2017)