Instruction buffering for nested loops in low-power design. - Chi Ta Wu; Ang-Chih Hsieh; TingTing Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current. - Ang-Chih Hsieh; Tzu-Teng Lin; Tsuang-Wei Chang; TingTing Hwang (ACM Trans. Design Autom. Electr. Syst., 2007)

TSV redundancy: Architecture and design issues in 3D IC. - Ang-Chih Hsieh; TingTing Hwang; Ming-Tung Chang; Min-Hsiu Tsai; Chih-Mou Tseng; Hung-Chun Li (DATE, 2010)

Enhanced Heterogeneous Code Cache management scheme for Dynamic Binary Translation. - Ang-Chih Hsieh; Chun-Cheng Liu; TingTing Hwang (ASP-DAC, 2011)

Memory Mapping and Task Scheduling Techniques for Computation Models of Image Processing on Many-Core Platforms. - Ang-Chih Hsieh; Yi-Ta Wu; Shau-Yin Tseng; TingTing Hwang (ICPP, 2011)

TSV Redundancy: Architecture and Design Issues in 3-D IC. - Ang-Chih Hsieh; TingTing Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Run-Time Reconfiguration of Expandable Cache for Embedded Systems. - Ang-Chih Hsieh; TingTing Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Thermal-aware memory mapping in 3D designs. - Ang-Chih Hsieh; TingTing Hwang (ACM Trans. Embed. Comput. Syst., 2013)

Utilizing Circuit Structure for Scan Chain Diagnosis. - Wei-Hen Lo; Ang-Chih Hsieh; Chien-Ming Lan; Min-Hsien Lin; TingTing Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2014)