ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors. - Shuya Ji; Weidong Yang; Jianfei Jiang 001; Naifeng Jing; Weiguang Sheng; Ang Li 045; Qin Wang 009 (ICCD, 2023)

VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks. - Duo Yu; Ang Li 045; Naifeng Jing; Jianfei Jiang 001; Weiguang Sheng; Qin Wang 009 (ACM Great Lakes Symposium on VLSI, 2024)

A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined Execution in Spatial Programmable Architecture. - Pengyu Liu 004; Ang Li 045; Liyan Chen; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip. - Zizheng Dong; Shuaipeng Li; Weijia Zhu; Ang Li 045; Qin Wang 009; Naifeng Jing; Weiguang Sheng; Jianfei Jiang 001; Zhigang Mao (IEEE Trans. Very Large Scale Integr. Syst., 2025)