Submicrosecond Latency Video Compression in a Low-End FPGA-based System-on-Chip. - Tobias Alonso; Mario Ruiz; Angel Lopez Garcia-Arias; Gustavo Sutter; Jorge E. López de Vergara (FPL, 2018)

Low-Cost Reservoir Computing using Cellular Automata and Random Forests. - Ángel López García-Arias; Jaehoon Yu; Masanori Hashimoto (ISCAS, 2020)

Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. - Ángel López García-Arias; Masanori Hashimoto; Masato Motomura; Jaehoon Yu (BMVC, 2021)

Multicoated Supermasks Enhance Hidden Networks. - Yasuyuki Okoshi; Ángel López García-Arias; Kazutoshi Hirose; Kota Ando; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (ICML, 2022)

Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet. - Kazutoshi Hirose; Jaehoon Yu; Kota Ando; Yasuyuki Okoshi; Ángel López García-Arias; Junnosuke Suzuki; Thiem Van Chu; Kazushi Kawamura; Masato Motomura (ISSCC, 2022)

Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension. - Kazushi Kawamura; Jaehoon Yu; Daiki Okonogi; Satoru Jimbo; Genta Inoue; Akira Hyodo; Ángel López García-Arias; Kota Ando; Bruno Hideki Fukushima-Kimura; Ryota Yasudo; Thiem Van Chu; Masato Motomura (ISSCC, 2023)

Multicoated and Folded Graph Neural Networks With Strong Lottery Tickets. - Jiale Yan; Hiroaki Ito; Ángel López García-Arias; Yasuyuki Okoshi; Hikari Otsuka; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (LoG, 2023)

Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. - Junnosuke Suzuki; Jaehoon Yu; Mari Yasunaga; Ángel López García-Arias; Yasuyuki Okoshi; Shungo Kumazawa; Kota Ando; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (VLSI Technology and Circuits, 2023)

Recurrent Residual Networks Contain Stronger Lottery Tickets. - Ángel López García-Arias; Yasuyuki Okoshi; Masanori Hashimoto; Masato Motomura; Jaehoon Yu (IEEE Access, 2023)

WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression. - Yasuyuki Okoshi; Ángel López García-Arias; Jaehoon Yu; Junnosuke Suzuki; Hikari Otsuka; Thiem Van Chu; Kazushi Kawamura; Daichi Fujiki; Masato Motomura (A-SSCC, 2024)

Exploiting N:M Sparsity in Quantized-Folded ResNets: Signed Multicoat Supermasks and Iterative Pruning-Quantization. - Akihiro Shioda; Ángel López García-Arias; Hikari Otsuka; Yuki Ichikawa; Yasuyuki Okoshi; Kazushi Kawamura; Thiem Van Chu; Daichi Fujiki; Masato Motomura (CANDAR, 2024)

Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision. - Junnosuke Suzuki; Jaehoon Yu; Mari Yasunaga; Ángel López García-Arias; Yasuyuki Okoshi; Shungo Kumazawa; Kota Ando; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (IEEE Access, 2024)

Partial Search in a Frozen Network is Enough to Find a Strong Lottery Ticket. - Hikari Otsuka; Daiki Chijiwa; Ángel López García-Arias; Yasuyuki Okoshi; Kazushi Kawamura; Thiem Van Chu; Daichi Fujiki; Susumu Takeuchi; Masato Motomura (CoRR, 2024)

Restricted Random Pruning at Initialization for High Compression Range. - Hikari Otsuka; Yasuyuki Okoshi; Ángel López García-Arias; Kazushi Kawamura; Thiem Van Chu; Daichi Fujiki; Masato Motomura (Trans. Mach. Learn. Res., 2024)

WhiteDwarf: A Holistic Co-Design Approach to Ultra-Compact Neural Inference Acceleration. - Ángel López García-Arias; Yasuyuki Okoshi; Jaehoon Yu; Junnosuke Suzuki; Hikari Otsuka; Kazushi Kawamura; Thiem Van Chu; Daichi Fujiki; Masato Motomura (IEEE Access, 2025)

Partially Frozen Random Networks Contain Compact Strong Lottery Tickets. - Hikari Otsuka; Daiki Chijiwa; Ángel López García-Arias; Yasuyuki Okoshi; Kazushi Kawamura; Thiem Van Chu; Daichi Fujiki; Susumu Takeuchi; Masato Motomura (Trans. Mach. Learn. Res., 2025)