VLSI configurable delay commutator for a pipeline split radix FFT architecture. - Jesús García; Juan A. Michell; Angel M. Burón (IEEE Trans. Signal Process., 1999)

Parallel-pipelined architecture for 2-D ICT VLSI implementation. - Juan A. Michell; Gustavo A. Ruiz; Angel M. Burón (ICIP (3), 2003)

High throughput 2D DCT/IDCT processor for video coding. - Gustavo A. Ruiz; Juan A. Michell; Angel M. Burón (ICIP (3), 2005)

Parallel-pipeline 8×8 forward 2-D ICT processor chip for image coding. - Gustavo A. Ruiz; Juan A. Michell; Angel M. Burón (IEEE Trans. Signal Process., 2005)

High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip. - Gustavo A. Ruiz; Juan A. Michell; Angel M. Burón (J. VLSI Signal Process., 2006)

Haar wavelet based processor scheme for image coding with low circuit complexity. - F. Javier Díaz; Angel M. Burón; José M. Solana (Comput. Electr. Eng., 2007)