Generation of high quality tests for functional sensitizable paths. - Angela Krstic; Kwang-Ting Cheng (VTS, 1995)

Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability. - Angela Krstic; Kwang-Ting Cheng (ED&TC, 1996)

Identification and Test Generation for Primitive Faults. - Angela Krstic; Kwang-Ting Cheng; Srimat T. Chakradhar (ITC, 1996)

Generation of High Quality Tests for Robustly Untestable Path Delay Faults. - Kwang-Ting Cheng; Angela Krstic; Hsi-Chuan Chen (IEEE Trans. Computers, 1996)

Post-Layout Logic Restructuring for Performance Optimization. - Yi-Min Jiang; Angela Krstic; Kwang-Ting Cheng; Malgorzata Marek-Sadowska (DAC, 1997)

Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits. - Angela Krstic; Kwang-Ting Cheng (DAC, 1997)

Design for Primitive Delay Fault Testability. - Angela Krstic; Kwang-Ting Cheng; Srimat T. Chakradhar (ITC, 1997)

Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability. - Angela Krstic; Kwang-Ting Cheng (J. Electron. Test., 1997)

Delay testing considering power supply noise effects. - Yi-Min Jiang; Angela Krstic; Kwang-Ting Cheng (ITC, 1999)

Testing High Speed VLSI Devices Using Slower Testers. - Angela Krstic; Kwang-Ting (Tim) Cheng; Srimat T. Chakradhar (VTS, 1999)

Current Directions in Automatic Test-Pattern Generation. - Kwang-Ting Cheng; Angela Krstic (Computer, 1999)

Primitive delay faults: identification, testing, and design for testability. - Angela Krstic; Kwang-Ting Cheng; Srimat T. Chakradhar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Performance sensitivity analysis using statistical method and its applications to delay. - Jing-Jia Liou; Angela Krstic; Kwang-Ting Cheng; Deb Aditya Mukherjee; Sandip Kundu (ASP-DAC, 2000)

Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. - Jing-Jia Liou; Angela Krstic; Yi-Min Jiang; Kwang-Ting Cheng (ICCAD, 2000)

Dynamic Timing Analysis Considering Power Supply Noise Effects. - Yi-Min Jiang; Angela Krstic; Kwang-Ting Cheng (ISQED, 2000)

Test program synthesis for path delay faults in microprocessor cores. - Wei-Cheng Lai; Angela Krstic; Kwang-Ting Cheng (ITC, 2000)

On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set. - Wei-Cheng Lai; Angela Krstic; Kwang-Ting Cheng (VTS, 2000)

Functionally Testable Path Delay Faults on a Microprocessor. - Wei-Cheng Lai; Angela Krstic; Kwang-Ting (Tim) Cheng (IEEE Des. Test Comput., 2000)

Testable Path Delay Fault Cover for Sequential Circuits. - Angela Krstic; Srimat T. Chakradhar; Kwang-Ting Cheng (J. Inf. Sci. Eng., 2000)

Estimation for maximum instantaneous current through supply lines for CMOS circuits. - Yi-Min Jiang; Angela Krstic; Kwang-Ting Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Fast Statistical Timing Analysis By Probabilistic Event Propagation. - Jing-Jia Liou; Kwang-Ting Cheng; Sandip Kundu; Angela Krstic (DAC, 2001)

Delay testing considering crosstalk-induced effects. - Angela Krstic; Jing-Jia Liou; Yi-Min Jiang; Kwang-Ting Cheng (ITC, 2001)

Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects. - Angela Krstic; Yi-Min Jiang; Kwang-Ting Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Embedded software-based self-testing for SoC design. - Angela Krstic; Wei-Cheng Lai; Kwang-Ting Cheng; Li Chen; Sujit Dey (DAC, 2002)

False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. - Jing-Jia Liou; Angela Krstic; Li-C. Wang; Kwang-Ting Cheng (DAC, 2002)

Embedded Software-Based Self-Test for Programmable Core-Based Designs. - Angela Krstic; Wei-Cheng Lai; Kwang-Ting Cheng; Li Chen; Sujit Dey (IEEE Des. Test Comput., 2002)

Experience in critical path selection for deep sub-micron delay test and timing validation. - Jing-Jia Liou; Li-C. Wang; Angela Krstic; Kwang-Ting Cheng (ASP-DAC, 2003)

Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. - Angela Krstic; Li-C. Wang; Kwang-Ting Cheng; Jing-Jia Liou; T. M. Mak (DAC, 2003)

Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. - Angela Krstic; Li-C. Wang; Kwang-Ting Cheng; Jing-Jia Liou; Magdy S. Abadir (DATE, 2003)

On Structural vs. Functional Testing for Delay Faults. - Angela Krstic; Jing-Jia Liou; Kwang-Ting Cheng; Li-C. Wang (ISQED, 2003)

HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk. - Xiaoliang Bai; Sujit Dey; Angela Krstic (ITC, 2003)

Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies. - Angela Krstic; Li-C. Wang; Kwang-Ting Cheng; T. M. Mak (ITC, 2003)

Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. - Li-C. Wang; Angela Krstic; Leonard Lee; Kwang-Ting Cheng; M. Ray Mercer; Thomas W. Williams; Magdy S. Abadir (ITC, 2003)

Diagnosis of Delay Defects Using Statistical Timing Models. - Angela Krstic; Li-C. Wang; Kwang-Ting Cheng; Jing-Jia Liou (VTS, 2003)

Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation. - Jing-Jia Liou; Li-C. Wang; Angela Krstic; Kwang-Ting (Tim) Cheng (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. - Jing-Jia Liou; Angela Krstic; Yi-Min Jiang; Kwang-Ting Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

New Challenges in Delay Testing of Nanometer, Multigigahertz Designs. - T. M. Mak; Angela Krstic; Kwang-Ting (Tim) Cheng; Li-C. Wang (IEEE Des. Test Comput., 2004)