A 200-MSample/s trellis-coded PRML read/write channel with analog adaptive equalizer and digital servo. - Roberto Alini; Giorgio Betti; Ivan Bietti; Giacomino Bollati; Francesco Brianti; Angelo Dati; Marco Demicheli; Paolo Gadducci; Stefano Marchese; Emanuele Marconetti; Valerio Pisati; Maurizio Zuffada; et al. (IEEE J. Solid State Circuits, 1997)

A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi. - Giacomino Bollati; Angelo Dati; Giorgio Betti; Ivan Bietti; Francesco Brianti; Melchiorre Bruccoleri; M. Coltella; P. Demartini; Marco Demicheli; Paolo Gadducci; Stefano Marchese; Daniele Ottini; et al. (CICC, 2000)

8.3 A power-scalable 7-tap FIR equalizer with tunable active delay line for 10-to-25Gb/s multi-mode fiber EDC in 28nm LP-CMOS. - Enrico Mammei; Fabrizio Loi; Francesco Radice; Angelo Dati; Melchiorre Bruccoleri; Matteo Bassi; Andrea Mazzanti (ISSCC, 2014)

Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS. - Enrico Mammei; Fabrizio Loi; Francesco Radice; Angelo Dati; Melchiorre Bruccoleri; Matteo Bassi; Andrea Mazzanti (IEEE J. Solid State Circuits, 2014)