DORY: Lightweight memory hierarchy management for deep NN inference on IoT endnodes: work-in-progress. - Alessio Burrello; Francesco Conti 001; Angelo Garofalo; Davide Rossi; Luca Benini (CODES+ISSS, 2019)

On-line Testing for Autonomous Systems driven by RISC-V Processor Design Verification. - Annachiara Ruospo; Riccardo Cantoro; Ernesto Sánchez 001; Pasquale Davide Schiavone; Angelo Garofalo; Luca Benini (DFT, 2019)

PULP-NN: A Computing Library for Quantized Neural Network inference at the edge on RISC-V Based Parallel Ultra Low Power Clusters. - Angelo Garofalo; Manuele Rusci; Francesco Conti 001; Davide Rossi; Luca Benini (ICECS, 2019)

PULP-NN: Accelerating Quantized Neural Networks on Parallel Ultra-Low-Power RISC-V Processors. - Angelo Garofalo; Manuele Rusci; Francesco Conti 001; Davide Rossi; Luca Benini (CoRR, 2019)

Enabling mixed-precision quantized neural networks in extreme-edge devices. - Nazareno Bruschi; Angelo Garofalo; Francesco Conti 001; Giuseppe Tagliavini; Davide Rossi (CF, 2020)

XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions. - Angelo Garofalo; Giuseppe Tagliavini; Francesco Conti 001; Davide Rossi; Luca Benini (DATE, 2020)

A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. - Gianmarco Ottavi; Angelo Garofalo; Giuseppe Tagliavini; Francesco Conti 001; Luca Benini; Davide Rossi (ISVLSI, 2020)

A transprecision floating-point cluster for efficient near-sensor data analytics. - Fabio Montagna; Stefan Mach; Simone Benatti; Angelo Garofalo; Gianmarco Ottavi; Luca Benini; Davide Rossi; Giuseppe Tagliavini (CoRR, 2020)

XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes. - Angelo Garofalo; Giuseppe Tagliavini; Francesco Conti 001; Luca Benini; Davide Rossi (CoRR, 2020)

Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-core MCUs. - Fabio Montagna; Giuseppe Tagliavini; Davide Rossi; Angelo Garofalo; Luca Benini (ARCS, 2021)

A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. - Angelo Garofalo; Gianmarco Ottavi; Alfio Di Mauro; Francesco Conti 001; Giuseppe Tagliavini; Luca Benini; Davide Rossi (ESSCIRC, 2021)

DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs. - Alessio Burrello; Angelo Garofalo; Nazareno Bruschi; Giuseppe Tagliavini; Davide Rossi; Francesco Conti 001 (IEEE Trans. Computers, 2021)

XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes. - Angelo Garofalo; Giuseppe Tagliavini; Francesco Conti 001; Luca Benini; Davide Rossi (IEEE Trans. Emerg. Top. Comput., 2021)

Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training. - Angelo Garofalo; Matteo Perotti; Luca Valente; Yvan Tortorella; Alessandro Nadalini; Luca Benini; Davide Rossi; Francesco Conti 001 (ESSCIRC, 2022)

A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference. - Manuel Le Gallo; Riduan Khaddam-Aljameh; Milos Stanisavljevic; Athanasios Vasilopoulos; Benedikt Kersting; Martino Dazzi; Geethan Karunaratne; Matthias Braendli; Abhairaj Singh; Silvia M. Mueller; Julian Büchel; Xavier Timoneda Comas; et al. (CoRR, 2022)

A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks. - Angelo Garofalo; Gianmarco Ottavi; Francesco Conti 001; Geethan Karunaratne; Irem Boybat; Luca Benini; Davide Rossi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics. - Fabio Montagna; Stefan Mach; Simone Benatti; Angelo Garofalo; Gianmarco Ottavi; Luca Benini; Davide Rossi; Giuseppe Tagliavini (IEEE Trans. Parallel Distributed Syst., 2022)

End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture. - Nazareno Bruschi; Giuseppe Tagliavini; Angelo Garofalo; Francesco Conti 001; Irem Boybat; Luca Benini; Davide Rossi (DATE, 2023)

Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs. - Luca Valente; Asif Veeran; Mattia Sinigaglia; Yvan Tortorella; Alessandro Nadalini; Nils Wistoff; Bruno Sá; Angelo Garofalo; Rafail Psiakis; M. Tolba; Ari Kulmala; Nimisha Limaye; et al. (HCS, 2023)

Cyber Security aboard Micro Aerial Vehicles: An OpenTitan-based Visual Communication Use Case. - Maicol Ciani; Stefano Bonato; Rafail Psiakis; Angelo Garofalo; Luca Valente; Suresh Sugumar; Alessandro Giusti; Davide Rossi; Daniele Palossi (ISCAS, 2023)

ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays. - Mattia Sinigaglia; Luca Bertaccini; Luca Valente; Angelo Garofalo; Simone Benatti; Luca Benini; Francesco Conti 001; Davide Rossi (ISCAS, 2023)

ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized Transformers. - Gamze Islamoglu; Moritz Scherer 001; Gianna Paulin; Tim Fischer 001; Victor J. B. Jung; Angelo Garofalo; Luca Benini (ISLPED, 2023)

A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing. - Francesco Conti 001; Davide Rossi; Gianna Paulin; Angelo Garofalo; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggimann; Hayate Okuhara; Vincent Huard; Olivier Montfort; Lionel Jure; et al. (ISSCC, 2023)

A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks. - Alessandro Nadalini; Georg Rutishauser; Alessio Burrello; Nazareno Bruschi; Angelo Garofalo; Luca Benini; Francesco Conti 001; Davide Rossi (ISVLSI, 2023)

DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training. - Angelo Garofalo; Yvan Tortorella; Matteo Perotti; Luca Valente; Alessandro Nadalini; Luca Benini; Davide Rossi; Francesco Conti 001 (CoRR, 2023)

Echoes: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays. - Mattia Sinigaglia; Luca Bertaccini; Luca Valente; Angelo Garofalo; Simone Benatti; Luca Benini; Francesco Conti 001; Davide Rossi (CoRR, 2023)

Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. - Gianmarco Ottavi; Angelo Garofalo; Giuseppe Tagliavini; Francesco Conti 001; Alfio Di Mauro; Luca Benini; Davide Rossi (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems. - Chaoqun Liang; Alessandro Ottaviano; Thomas Benz; Mattia Sinigaglia; Luca Benini; Angelo Garofalo; Davide Rossi (CF (Companion), 2024)

AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs. - Thomas Benz; Alessandro Ottaviano; Robert Balas; Angelo Garofalo; Francesco Restuccia 002; Alessandro Biondi 001; Luca Benini (DATE, 2024)

vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-Criticality Systems. - Enrico Zelioli; Alessandro Ottaviano; Robert Balas; Nils Wistoff; Angelo Garofalo; Luca Benini (ICCD, 2024)

SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications. - Michael Rogenmoser; Alessandro Ottaviano; Thomas Benz; Robert Balas; Matteo Perotti; Angelo Garofalo; Luca Benini (CoRR, 2024)

Unleashing OpenTitan's Potential: a Silicon-Ready Embedded Secure Element for Root of Trust and Cryptographic Offloading. - Maicol Ciani; Emanuele Parisi; Alberto Musa; Francesco Barchi; Andrea Bartolini; Ari Kulmala; Rafail Psiakis; Angelo Garofalo; Andrea Acquaviva; Davide Rossi (CoRR, 2024)

A Flexible Template for Edge Generative AI with High-Accuracy Accelerated Softmax & GELU. - Andrea Belano; Yvan Tortorella; Angelo Garofalo; Luca Benini; Davide Rossi; Francesco Conti 001 (CoRR, 2024)

Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience. - Francesco Conti 001; Angelo Garofalo; Davide Rossi; Giuseppe Tagliavini; Luca Benini (CoRR, 2024)

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing. - Francesco Conti 001; Gianna Paulin; Angelo Garofalo; Davide Rossi; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggimann; Hayate Okuhara; Luca Benini (IEEE J. Solid State Circuits, 2024)

VEXP: A Low-Cost RISC-V ISA Extension for Accelerated Softmax Computation in Transformers. - Run Wang; Gamze Islamoglu; Andrea Belano; Viviane Potocnik; Francesco Conti 001; Angelo Garofalo; Luca Benini (ARITH, 2025)

MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products. - Gamze Islamoglu; Luca Bertaccini; Arpan Suravi Prasad; Francesco Conti 001; Angelo Garofalo; Luca Benini (ASAP, 2025)

Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications. - Danilo Cammarata; Matteo Perotti; Marco Bertuletti; Angelo Garofalo; Pasquale Davide Schiavone; David Atienza; Luca Benini (CF (Companion), 2025)

FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators. - Victor Isachi; Alessandro Nadalini; Riccardo Fiorani Gallotta; Angelo Garofalo; Francesco Conti 001; Davide Rossi (CF, 2025)

CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor. - Christopher Reinwardt; Robert Balas; Alessandro Ottaviano; Angelo Garofalo; Luca Benini (CF, 2025)

RedMulE-FT: A Reconfigurable Fault-Tolerant Matrix Multiplication Engine. - Philip Wiese; Maurus Item; Luca Bertaccini; Yvan Tortorella; Angelo Garofalo; Luca Benini (CF (Companion), 2025)

SoftEx: A Low Power and Flexible Softmax Accelerator with Fast Approximate Exponentiation. - Andrea Belano; Yvan Tortorella; Angelo Garofalo; Luca Benini; Davide Rossi; Francesco Conti 001 (DATE, 2025)

Towards Reliable Systems: A Scalable Approach to AXI4 Transaction Monitoring. - Chaoqun Liang; Thomas Benz; Alessandro Ottaviano; Angelo Garofalo; Luca Benini; Davide Rossi (DATE, 2025)

Multi-Mode Borderguard Controllers for Efficient On-Chip Communication in Heterogeneous Digital/Analog Neural Processing Units. - Hong Pang; Carmine Cappetta; Riccardo Massa; Athanasios Vasilopoulos; Elena Ferro; Gamze Islamoglu; Angelo Garofalo; Francesco Conti 001; Luca Benini; Irem Boybat; Thomas Boesch (DATE, 2025)

Multi-Partner Project: Architectures and Design Methodologies to Accelerate AI Workloads. The ICSC Flagship 2 Project. - Cristina Silvano; Fabrizio Ferrandi; Serena Curzel; Daniele Ielmini; Stefania Perri; Fanny Spagnolo; Pasquale Corsonello; Sebastiano Fabio Schifano; Cristian Zambelli; Angelo Garofalo; Francesco Conti 001; Luca Benini (DATE, 2025)

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. - Angelo Garofalo; Alessandro Ottaviano; Matteo Perotti; Thomas Benz; Yvan Tortorella; Robert Balas; Michael Rogenmoser; Chi Zhang; Luca Bertaccini; Nils Wistoff; Maicol Ciani; Cyril Koenig; et al. (CoRR, 2025)

A Flexible Template for Edge Generative AI With High-Accuracy Accelerated Softmax and GELU. - Andrea Belano; Yvan Tortorella; Angelo Garofalo; Luca Benini; Davide Rossi; Francesco Conti 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2025)

relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication. - Michael Rogenmoser; Angelo Garofalo; Luca Benini (CoRR, 2025)

AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems. - Thomas Benz; Alessandro Ottaviano; Chaoqun Liang; Robert Balas; Angelo Garofalo; Francesco Restuccia 002; Alessandro Biondi 001; Davide Rossi; Luca Benini (IEEE Trans. Computers, 2025)

Leveraging RISC-V for HW/SW Codesign of Flexible and Efficient TinyML SoCs. - Angelo Garofalo; Luca Benini (IEEE Des. Test, 2025)

A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. - Cristina Silvano; Daniele Ielmini; Fabrizio Ferrandi; Leandro Fiorin; Serena Curzel; Luca Benini; Francesco Conti 001; Angelo Garofalo; Cristian Zambelli; Enrico Calore; Sebastiano Fabio Schifano; Maurizio Palesi; et al. (ACM Comput. Surv., 2025)