17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter. - Mario Mercandelli; Alessio Santiccioli; Angelo Parisi; Luca Bertulessi; Dmytro Cherniak; Andrea Leonardo Lacaita; Carlo Samori; Salvatore Levantino (ISSCC, 2020)

17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking. - Alessio Santiccioli; Mario Mercandelli; Luca Bertulessi; Angelo Parisi; Dmytro Cherniak; Andrea Leonardo Lacaita; Carlo Samori; Salvatore Levantino (ISSCC, 2020)

A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking. - Alessio Santiccioli; Mario Mercandelli; Luca Bertulessi; Angelo Parisi; Dmytro Cherniak; Andrea L. Lacaita; Carlo Samori; Salvatore Levantino (IEEE J. Solid State Circuits, 2020)

A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity. - Angelo Parisi; Mario Mercandelli; Carlo Samori; Andrea L. Lacaita (ICECS, 2021)

A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter. - Mario Mercandelli; Alessio Santiccioli; Simone Mattia Dartizio; Abanob Shehata; Francesco Tesolin; Saleh Karman; Luca Bertulessi; Francesco Buccoleri; Luca Avallone; Angelo Parisi; Andrea Leonardo Lacaita; Michael Peter Kennedy; et al. (ISSCC, 2021)

32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays. - Alessio Santiccioli; Mario Mercandelli; Simone Mattia Dartizio; Francesco Tesolin; Saleh Karman; Abanob Shehata; Luca Bertulessi; Francesco Buccoleri; Luca Avallone; Angelo Parisi; Dmytro Cherniak; Andrea L. Lacaita; et al. (ISSCC, 2021)

A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters. - Lorenzo Scaletti; Gabriele Bè; Angelo Parisi; Luca Bertulessi; Luca Ricci; Mario Mercandelli; Salvatore Levantino; Carlo Samori; Andrea Bonfanti (NEWCAS, 2022)

A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping. - Simone Mattia Dartizio; Francesco Tesolin; Mario Mercandelli; Alessio Santiccioli; Abanob Shehata; Saleh Karman; Luca Bertulessi; Francesco Buccoleri; Luca Avallone; Angelo Parisi; Andrea L. Lacaita; Michael Peter Kennedy; et al. (IEEE J. Solid State Circuits, 2022)

A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter. - Mario Mercandelli; Alessio Santiccioli; Angelo Parisi; Luca Bertulessi; Dmytro Cherniak; Andrea L. Lacaita; Carlo Samori; Salvatore Levantino (IEEE J. Solid State Circuits, 2022)

A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations. - Gabriele Bè; Angelo Parisi; Luca Bertulessi; Luca Ricci; Lorenzo Scaletti; Mario Mercandelli; Andrea L. Lacaita; Salvatore Levantino; Carlo Samori; Andrea Bonfanti (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Digitally assisted frequency synthesizers and data converters for wide-band radio systems. - Angelo Parisi (2022)