A technique for power reduction of CMOS circuit at 65nm technology. - Angshuman Chakraborty; Sambhu Nath Pradhan (RAIT, 2012)

Gate level leakage minimisation at 90 nm technology. - Angshuman Chakraborty; Sambhu Nath Pradhan (Int. J. Comput. Aided Eng. Technol., 2013)

Layout-oriented look up table-based dual threshold approach to reduce leakage. - Sambhu Nath Pradhan; Angshuman Chakraborty; Abhishek Nag; Debanjali Nath (Int. J. Comput. Aided Eng. Technol., 2015)