A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy. - Angshuman Parashar; Sudhanva Gurumurthi; Anand Sivasubramaniam (ISCA, 2004)

An uncalibrated lightfield acquisition system. - Puneet Sharma; Angshuman Parashar; Subhashis Banerjee; Prem Kumar Kalra (Image Vis. Comput., 2004)

SlicK: slice-based locality exploitation for efficient redundant multithreading. - Angshuman Parashar; Anand Sivasubramaniam; Sudhanva Gurumurthi (ASPLOS, 2006)

Mechanisms for bounding vulnerabilities of processor structures. - Niranjan Soundararajan; Angshuman Parashar; Anand Sivasubramaniam (ISCA, 2007)

Leap scratchpads: automatic memory and cache management for reconfigurable logic. - Michael Adler; Kermin Fleming; Angshuman Parashar; Michael Pellauer; Joel S. Emer (FPGA, 2011)

HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing. - Michael Pellauer; Michael Adler; Michel A. Kinsy; Angshuman Parashar; Joel S. Emer (HPCA, 2011)

Leveraging latency-insensitivity to ease multiple FPGA design. - Kermin Elliott Fleming; Michael Adler; Michael Pellauer; Angshuman Parashar; Arvind 001; Joel S. Emer (FPGA, 2012)

A Hierarchical Architectural Framework for Reconfigurable Logic Computing. - Peng Li 031; Angshuman Parashar; Michael Pellauer; Tao Wang 004; Joel S. Emer (IPDPS Workshops, 2013)

Triggered instructions: a control paradigm for spatially-programmed architectures. - Angshuman Parashar; Michael Pellauer; Michael Adler; Bushra Ahsan; Neal Clayton Crago; Daniel Lustig; Vladimir Pavlov; Antonia Zhai; Mohit Gambhir; Aamer Jaleel; Randy L. Allmon; Rachid Rayess; et al. (ISCA, 2013)

Efficient Spatial Processing Element Control via Triggered Instructions. - Angshuman Parashar; Michael Pellauer; Michael Adler; Bushra Ahsan; Neal Clayton Crago; Daniel Lustig; Vladimir Pavlov; Antonia Zhai; Mohit Gambhir; Aamer Jaleel; Randy L. Allmon; Rachid Rayess; et al. (IEEE Micro, 2014)

Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures. - Michael Pellauer; Angshuman Parashar; Michael Adler; Bushra Ahsan; Randy L. Allmon; Neal Clayton Crago; Kermin Fleming; Mohit Gambhir; Aamer Jaleel; Tushar Krishna; Daniel Lustig; Stephen Maresh; et al. (ACM Trans. Comput. Syst., 2015)

SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. - Angshuman Parashar; Minsoo Rhu; Anurag Mukkara; Antonio Puglielli; Rangharajan Venkatesan; Brucek Khailany; Joel S. Emer; Stephen W. Keckler; William J. Dally (ISCA, 2017)

Timeloop: A Systematic Approach to DNN Accelerator Evaluation. - Angshuman Parashar; Priyanka Raina; Yakun Sophia Shao; Yu-Hsin Chen; Victor A. Ying; Anurag Mukkara; Rangharajan Venkatesan; Brucek Khailany; Stephen W. Keckler; Joel S. Emer (ISPASS, 2019)

Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach. - Hyoukjun Kwon; Prasanth Chatarasi; Michael Pellauer; Angshuman Parashar; Vivek Sarkar; Tushar Krishna (MICRO, 2019)

MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings. - Hyoukjun Kwon; Prasanth Chatarasi; Vivek Sarkar; Tushar Krishna; Michael Pellauer; Angshuman Parashar (IEEE Micro, 2020)

Data Orchestration in Deep Learning Accelerators - Tushar Krishna; Hyoukjun Kwon; Angshuman Parashar; Michael Pellauer; Ananda Samajdar (Morgan & Claypool Publishers, 2020)

Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operations on Spatial Accelerators. - Geonhwa Jeong; Gokcen Kestor; Prasanth Chatarasi; Angshuman Parashar; Po-An Tsai; Sivasankaran Rajamanickam; Roberto Gioiosa; Tushar Krishna (PACT, 2021)

Mind mappings: enabling efficient algorithm-accelerator mapping space search. - Kartik Hegde; Po-An Tsai; Sitao Huang; Vikas Chandra; Angshuman Parashar; Christopher W. Fletcher (ASPLOS, 2021)

Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators. - Yannan Nellie Wu; Po-An Tsai; Angshuman Parashar; Vivienne Sze; Joel S. Emer (ISPASS, 2021)

Flexion: A Quantitative Metric for Flexibility in DNN Accelerators. - Hyoukjun Kwon; Michael Pellauer; Angshuman Parashar; Tushar Krishna (IEEE Comput. Archit. Lett., 2021)

DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators. - Sheng-Chun Kao; Michael Pellauer; Angshuman Parashar; Tushar Krishna (DATE, 2022)

Demystifying Map Space Exploration for NPUs. - Sheng-Chun Kao; Angshuman Parashar; Po-An Tsai; Tushar Krishna (IISWC, 2022)

Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization. - Mark Horeni; Pooria Taheri; Po-An Tsai; Angshuman Parashar; Joel S. Emer; Siddharth Joshi 001 (ISPASS, 2022)

Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling. - Yannan Nellie Wu; Po-An Tsai; Angshuman Parashar; Vivienne Sze; Joel S. Emer (MICRO, 2022)

Enabling Flexibility for Sparse Tensor Acceleration via Heterogeneity. - Eric Qin 001; Raveesh Garg; Abhimanyu Bambhaniya; Michael Pellauer; Angshuman Parashar; Sivasankaran Rajamanickam; Cong Hao; Tushar Krishna (CoRR, 2022)

A Formalism of DNN Accelerator Flexibility. - Sheng-Chun Kao; Hyoukjun Kwon; Michael Pellauer; Angshuman Parashar; Tushar Krishna (Proc. ACM Meas. Anal. Comput. Syst., 2022)

Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators. - Prasanth Chatarasi; Hyoukjun Kwon; Angshuman Parashar; Michael Pellauer; Tushar Krishna; Vivek Sarkar (ACM Trans. Archit. Code Optim., 2022)

LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators. - Michael Gilbert; Yannan Nellie Wu; Angshuman Parashar; Vivienne Sze; Joel S. Emer (ISPASS, 2023)

HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity. - Yannan Nellie Wu; Po-An Tsai; Saurav Muralidharan; Angshuman Parashar; Vivienne Sze; Joel S. Emer (MICRO, 2023)

Mind the Gap: Attainable Data Movement and Operational Intensity Bounds for Tensor Algorithms. - Qijing Huang 001; Po-An Tsai; Joel S. Emer; Angshuman Parashar (ISCA, 2024)