Continuous-time adaptive-analog coaxial cable equalizer in 0.5 um CMOS. - G. P. Hartman; Kenneth W. Martin; Angus McLaren (ISCAS (2), 1999)

Generation of accurate on-chip time-constants using a monolithic CMOS PLL with hybrid analog and digital control. - Angus McLaren; Kenneth W. Martin (ISCAS, 2000)

Generation of accurate on-chip time constants and stable transconductances. - Angus McLaren; Ken Martin (IEEE J. Solid State Circuits, 2001)

An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology. - Mehrdad Ramezani; Mohamed Abdalla; Ayal Shoval; Marcus van Ierssel; Afshin Rezayee; Angus McLaren; Chris D. Holdenried; Jennifer Pham; Eric So; David Cassan; Saman Sadr (ISSCC, 2011)

A low jitter 2.7mW/Gbps 180Gb/s 12-lane transmitter in a 40nm CMOS technology. - Kamran Farzan; Mehrdad Ramezani; Angus McLaren; Roman Pahuta; Nadeesha Amarasinghe; David Cassan; Saman Sadr (ESSCIRC, 2012)

A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support. - Mohammad Sadegh Jalali; Mohammad Hossein Taghavi; Angus McLaren; Jennifer Pham; Kamran Farzan; Dominic DiClemente; Marcus van Ierssel; William Song; Saman Asgaran; Chris D. Holdenried; Saman Sadr (ISSCC, 2018)

11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS. - Ravi Shivnaraine; Marcus van Ierssel; Kamran Farzan; Dominic DiClemente; George Ng; Nanyan Wang; Javid Musayev; Gairik Dutta; Masumi Shibata; Arash Moradi; Haleh Vahedi; Manavi Farzad; et al. (ISSCC, 2021)