A full current-mode sense amplifier for low-power SRAM applications. - Anh-Tuan Do; Jeremy Yung Shern Low; Zhi-Hui Kong; Kiat Seng Yeo; Joshua Yung Low Yung Lih (APCCAS, 2008)

Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing. - Anh-Tuan Do; Zhi-Hui Kong; Kiat Seng Yeo (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Low IR drop and low power parallel CAM design using gated power transistor technique. - Anh-Tuan Do; Shoushun Chen; Zhi-Hui Kong; Kiat Seng Yeo (APCCAS, 2010)

An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving. - Anh-Tuan Do; Kiat Seng Yeo; Jeremy Yung Shern Low; Joshua Yung Lih Low; Zhi-Hui Kong (APCCAS, 2010)

A 16Kb 10T-SRAM with 4x read-power reduction. - Zhi-Hui Kong; Anh-Tuan Do (ISCAS, 2010)

Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier. - Anh-Tuan Do; Zhi-Hui Kong; Kiat Seng Yeo (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A new match line sensing technique in Content Addressable Memory. - Xiaoliang Tan; Anh-Tuan Do; Shoushun Chen; Kiat Seng Yeo; Zhi-Hui Kong (COOL Chips, 2011)

A comparative study of state-of-the-art low-power CAM match-line sense amplifier designs. - Anh-Tuan Do; Xiaoliang Tan; Shoushun Chen; Zhi-Hui Kong; Kiat Seng Yeo (ACM Great Lakes Symposium on VLSI, 2011)

A low-power CAM with efficient power and delay trade-off. - Anh-Tuan Do; Shoushun Chen; Zhi-Hui Kong; Kiat Seng Yeo (ISCAS, 2011)

Adaptive priority toggle asynchronous tree arbiter for AER-based image sensor. - Myat Thu Linn Aung; Anh-Tuan Do; Shoushun Chen; Kiat Seng Yeo (VLSI-SoC, 2011)

An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS. - Anh-Tuan Do; Jeremy Yung Shern Low; Joshua Yung Lih Low; Zhi-Hui Kong; Xiaoliang Tan; Kiat Seng Yeo (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM. - Anh-Tuan Do; Zhi-Hui Kong; Kiat Seng Yeo; Jeremy Yung Shern Low (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Modeling and optimization of a combined cooling, heating and power plant system. - Vikas Chandan; Anh-Tuan Do; Baoduo Jin; Faryar Jabbari; Jack Brouwer; Ioannis Akrotirianakis; Amit Chakraborty; Andrew G. Alleyne (ACC, 2012)

A 9.87 nW 1 kS/s 8.7 ENOB SAR ADC for implantable epileptic seizure detection microsystems. - Anh-Tuan Do; Chun Kit Lam; Yung Sern Tan; Kiat Seng Yeo; Jia Hao Cheong; Lei Yao; Meng Tong Tan; Minkyu Je (APCCAS, 2012)

Low power implantable neural recording front-end. - Anh-Tuan Do; Yung Sern Tan; Chun Kit Lam; Minkyu Je; Kiat Seng Yeo (ISOCC, 2012)

High energy efficient ultra-low voltage SRAM design: Device, circuit, and architecture. - Tony T. Kim; Bo Wang 020; Anh-Tuan Do (ISOCC, 2012)

A 57∼66GHz CMOS voltage-controlled oscillator using tunable differential inductor. - Haitao Wang; Kiat Seng Yeo; Anh-Tuan Do; Yung Sern Tan; Kai Kang; Zhenghao Lu (ISOCC, 2012)

A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications. - Anh-Tuan Do; Chun Kit Lam; Yung Sern Tan; Kiat Seng Yeo; Jia Hao Cheong; Xiaodan Zou; Lei Yao; Kuang-Wei Cheng; Minkyu Je (NEWCAS, 2012)

Sensing Margin Enhancement Techniques for Ultra-Low-Voltage SRAMs Utilizing a Bitline-Boosting Current and Equalized Bitline Leakage. - Anh-Tuan Do; Truc Quynh Nguyen; Kiat Seng Yeo; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Design of a power-efficient CAM using automated background checking scheme for small match line swing. - Anh Tuan Do; Chun Yin; Kiat Seng Yeo; Tony Tae-Hyoung Kim (ESSCIRC, 2013)

Design and array implementation a cantilever-based non-volatile memory utilizing vibrational reset. - Anh-Tuan Do; Karthik G. Jayaraman; Pushpapraj Singh; Chua Geng Li; Kiat Seng Yeo; Tony Tae-Hyoung Kim (ESSDERC, 2013)

An improved read/write scheme for anchorless NEMS-CMOS non-volatile memory. - Anh-Tuan Do; Karthik G. Jayaraman; Vincent Pott; Chua Geng Li; Pushpapraj Singh; Kiat Seng Yeo; Tony Tae-Hyoung Kim (ISCAS, 2013)

A current-mode stimulator circuit with two-step charge balancing background calibration. - Anh-Tuan Do; Yung Sern Tan; Gordon M. Xiong; Cleo Choong; Zhi-Hui Kong; Kiat Seng Yeo (ISCAS, 2013)

A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing. - Anh-Tuan Do; Shoushun Chen; Zhi-Hui Kong; Kiat Seng Yeo (IEEE Trans. Very Large Scale Integr. Syst., 2013)

0.2 V 8T SRAM with improved bitline sensing using column-based data randomization. - Anh-Tuan Do; Zhao Chuan Lee; Bo Wang 020; Ik-Joon Chang; Tony Tae-Hyoung Kim (A-SSCC, 2014)

A hybrid NEO-based spike detection algorithm for implantable brain-IC interface applications. - Anh-Tuan Do; Kiat Seng Yeo (ISCAS, 2014)

Internet of Things: Trends, challenges and applications. - Kiat Seng Yeo; Mojy Curtis Chian; Tony Chon Wee Ng; Anh-Tuan Do (ISIC, 2014)

0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance. - Anh-Tuan Do; Chun Yin; Kavitha Velayudhan; Zhao Chuan Lee; Kiat Seng Yeo; Tony Tae-Hyoung Kim (IEEE J. Solid State Circuits, 2014)

A 32kb 9T SRAM with PVT-tracking read margin enhancement for ultra-low voltage operation. - Anh-Tuan Do; Kiat Seng Yeo; Tony Tae-Hyoung Kim (ISCAS, 2015)

Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits. - Seyed Mohammad Ali Zeinolabedin; Anh-Tuan Do; Kiat Seng Yeo; Tony Tae-Hyoung Kim (ISCAS, 2015)

Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement. - Bo Wang 020; Truc Quynh Nguyen; Anh-Tuan Do; Jun Zhou 017; Minkyu Je; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm2 per Channel in 65-nm CMOS. - Seyed Mohammad Ali Zeinolabedin; Anh-Tuan Do; Dongsuk Jeon; Dennis Sylvester; Tony Tae-Hyoung Kim (APCCAS, 2016)

A 0.3 pJ/access 8T data-aware SRAM utilizing column-based data encoding for ultra-low power applications. - Anh-Tuan Do; Seyed Mohammad Ali Zeinolabedin; Tony Tae-Hyoung Kim (A-SSCC, 2016)

A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm2 per channel in 65-nm CMOS. - Seyed Mohammad Ali Zeinolabedin; Anh-Tuan Do; Dongsuk Jeon; Dennis Sylvester; Tony Tae-Hyoung Kim (VLSI Circuits, 2016)

0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization. - Anh-Tuan Do; Zhao Chuan Lee; Bo Wang 020; Ik-Joon Chang; Xin Liu 015; Tony Tae-Hyoung Kim (IEEE J. Solid State Circuits, 2016)

25 fJ/bit, 5Mb/s, 0.3 V true random number generator with capacitively-coupled chaos system and dual-edge sampling scheme. - Anh-Tuan Do; Xin Liu 015 (A-SSCC, 2017)

0.54 pJ/bit, 15Mb/s True Random Number Generator Using Probabilistic Delay Cell for Edge Computing Applications. - Fei Li 015; Ming Ming Wong; Aarthy Mani; Vishnu Paramasivam; Anh-Tuan Do (A-SSCC, 2019)

Block-Based Spiking Neural Network Hardware with Deme Genetic Algorithm. - Junran Pu; Vishnu P. Nambiar; Anh-Tuan Do; Wang Ling Goh (ISCAS, 2019)

0.8% BER 1.2 pJ/bit Arbiter-based PUF for Edge Computing Using Phase-Difference Accumulation Technique. - Anh-Tuan Do (SoCC, 2019)

Coverage Driven Verification Methodology for Asynchronous Neuromorphic Routers. - Yun Kwan Lee; Vishnu P. Nambiar; Junran Pu; Wang Ling Goh; Anh-Tuan Do (SoCC, 2019)

Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing. - Junran Pu; Vishnu P. Nambiar; Aarthy Mani; Wang Ling Goh; Anh-Tuan Do (SoCC, 2019)

Folded and Deterministic Stochastic MAC for High Accuracy and Hardware Efficient Convolution Function. - Ming Ming Wong; Anh-Tuan Do (SoCC, 2019)

A Wireless Multi-Channel Peripheral Nerve Signal Acquisition System-on-Chip. - Kian Ann Ng; Chao Yuan; Astrid Rusly; Anh-Tuan Do; Bin Zhao; Shih-Chiang Liu; Wendy Yen Xian Peh; Thow Xin Yuan; Kai Voges; Sanghoon Lee 010; Gil Gerald Lasam Gammad; Khay-Wai Leong; et al. (IEEE J. Solid State Circuits, 2019)

An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS. - Anh-Tuan Do; Seyed Mohammad Ali Zeinolabedin; Dongsuk Jeon; Dennis Sylvester; Tony Tae-Hyoung Kim (IEEE Trans. Very Large Scale Integr. Syst., 2019)

0.5V 4.8 pJ/SOP 0.93µW Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron. - Vishnu P. Nambiar; Junran Pu; Yun Kwan Lee; Aarthy Mani; Tao Luo 014; L. Yang; Eng-Kiat Koh; Ming Ming Wong; Fei Li 015; Wang Ling Goh; Anh Tuan Do (A-SSCC, 2020)

NCPower: Power Modelling for NVM-based Neuromorphic Chip. - Zhehui Wang; Huaipeng Zhang; Tao Luo 014; Weng-Fai Wong; Anh-Tuan Do; Paramasivam Vishnu; Wei Zhang 012; Rick Siow Mong Goh (ICONS, 2020)

Aggressive Leakage Current Reduction for Embedded MRAM Using Block-Level Power Gating. - Anh Tuan Do; Xuanyao Fong; Fei Li 015 (IECON, 2020)

Post-Silicon Validation Methodology for Resource-Constrained Neuromorphic Hardware. - Yun Kwan Lee; Vishnu P. Nambiar; Kim Seng Goh; Anh Tuan Do (IECON, 2020)

Area and Energy Efficient 2D Max-Pooling For Convolutional Neural Network Hardware Accelerator. - Bin Zhao; Yi Sheng Chong; Anh-Tuan Do (IECON, 2020)

Design and Characterization of Radiation-Hardened MCU for Space Application using Error Correction SRAM and Glitch Removal Clock Buffer Cell. - Anh Tuan Do; Tony Tae-Hyoung Kim; Xin Liu 015; Jun Zhou 017 (ISCAS, 2020)

Ultra-Low Leakage, High Fan-Out Neuro Connection Map with TCAM-Based LUT, Localized Priority Encoder and Decoder-Less SRAM. - Aarthy Mani; Fei Li 015; Ming Ming Wong; Luo Tao; Liwei Yang; Vishnu Paramasivam; Anh Tuan Do (ISCAS, 2020)

Scalable Block-Based Spiking Neural Network Hardware with a Multiplierless Neuron Model. - Vishnu P. Nambiar; Eng-Kiat Koh; Junran Pu; Aarthy Mani; Ming Ming Wong; Li Fei; Wang Ling Goh; Anh Tuan Do (ISCAS, 2020)

Energy-Efficient Data-Aware SRAM Design Utilizing Column-Based Data Encoding. - Anh-Tuan Do; Seyed Mohammad Ali Zeinolabedin; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Backpropagation Extreme Learning Machine Approach to Fast Training Neural Network-Based Side-Channel Attack. - Xuyang Huang; Ming Ming Wong; Anh Tuan Do; Wang Ling Goh (AsianHOST, 2021)

A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP. - Ming Ming Wong; S. B. Shrestha; Vishnu P. Nambiar; Aarthy Mani; Yun Kwan Lee; Eng-Kiat Koh; W. Jiang; Kevin Tshun Chuan Chai; Anh-Tuan Do (ESSDERC, 2021)

An Energy-Efficient Convolution Unit for Depthwise Separable Convolutional Neural Networks. - Yi Sheng Chong; Wang Ling Goh; Yew Soon Ong; Vishnu P. Nambiar; Anh Tuan Do (ISCAS, 2021)

Efficient Implementation of Activation Functions for LSTM accelerators. - Yi Sheng Chong; Wang Ling Goh; Yew Soon Ong; Vishnu P. Nambiar; Anh Tuan Do (VLSI-SoC, 2021)

A 25 TOPS/W High Power Efficiency Deterministic and Split Stochastic MAC (SC-MAC) Design. - Ming Ming Wong; Lu Chen; Anh Tuan Do (VLSI-SoC, 2021)

An Improved Deterministic Stochastic MAC (SC-MAC) for High Power Efficiency Design. - Ming Ming Wong; Lu Chen; Anh Tuan Do (VLSI-SoC (Selected Papers), 2021)

A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router. - Junran Pu; Wang Ling Goh; Vishnu P. Nambiar; Ming Ming Wong; Anh Tuan Do (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Energy Efficient 0.5V 4.8pJ/SOP 0.93μW Leakage/Core Neuromorphic Processor Design. - Vishnu P. Nambiar; Junran Pu; Yun Kwan Lee; Aarthy Mani; Eng-Kiat Koh; Ming Ming Wong; Fei Li 015; Wang Ling Goh; Anh Tuan Do (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Low-Cost High-Throughput Digital Design of Biorealistic Spiking Neuron. - Junran Pu; Wang Ling Goh; Vishnu P. Nambiar; Yi Sheng Chong; Anh Tuan Do (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Low Power and Low Area Router With Congestion-Aware Routing Algorithm for Spiking Neural Network Hardware Implementations. - Junran Pu; Wang Ling Goh; Vishnu P. Nambiar; Anh-Tuan Do (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

0.08mm2 128nW MFCC Engine for Ultra-low Power, Always-on Smart Sensing Applications. - Yi Sheng Chong; Wang Ling Goh; Yew Soon Ong; Vishnu P. Nambiar; Anh Tuan Do (ISCAS, 2022)

Recovering Accuracy of RRAM-based CIM for Binarized Neural Network via Chip-in-the-loop Training. - Yi Sheng Chong; Wang Ling Goh; Yew Soon Ong; Vishnu P. Nambiar; Anh Tuan Do (ISCAS, 2022)

A 1800μm2, 953Gbps/W AES Accelerator for IoT Applications in 40nm CMOS. - Jingjing Lan; Vishnu P. Nambiar; Ming Ming Wong; Fei Li 015; Yuan Gao 011; Kevin Tshun Chuan Chai; Anh Tuan Do (ISCAS, 2022)

Linearity Characterization of Hybrid Driving Scheme for Spatial Light Modulator System. - Z. Di; Aarthy Mani; Anh Tuan Do; A. Baranikov; R. M. Veetil; R. P. Domínguez; Arseniy I. Kuznetsov; Kevin T. C. Chai (ISOCC, 2022)

Noise-Aware and Lightweight LSTM for Keyword Spotting Applications. - Yingfeng Wang; Yi Sheng Chong; Wang Ling Goh; Anh Tuan Do (ISOCC, 2022)

Temperature Compensation on SRAM-Based Computation in Memory Array. - Qibang Zang; Wang Ling Goh; Fei Li 015; Lu Lu 013; Anh Tuan Do (ISOCC, 2022)

Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency. - Liwei Yang; Huaipeng Zhang; Tao Luo 014; Chuping Qu; Myat Thu Linn Aung; Yingnan Cui; Jun Zhou 014; Ming Ming Wong; Junran Pu; Anh Tuan Do; Rick Siow Mong Goh; Weng-Fai Wong (Neurocomputing, 2022)

Corrigendum to "Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency" [Neurocomputing (2022) 128-140]. - Liwei Yang; Huaipeng Zhang; Tao Luo 014; Chuping Qu; Myat Thu Linn Aung; Yingnan Cui; Jun Zhou 014; Ming Ming Wong; Junran Pu; Anh Tuan Do; Rick Siow Mong Goh; Weng-Fai Wong (Neurocomputing, 2022)

A 2.5 μW KWS Engine With Pruned LSTM and Embedded MFCC for IoT Applications. - Yi Sheng Chong; Wang Ling Goh; Vishnu P. Nambiar; Anh-Tuan Do (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

4b/4b/8b Precision Charge-Domain 8T-SRAM Based CiM for CNN Processing. - Qibang Zang; Wang Ling Goh; Yi Sheng Chong; Anh Tuan Do (AICAS, 2023)

A 129.83 TOPS/W Area Efficient Digital SOT/STT MRAM-Based Computing-In-Memory for Advanced Edge AI Chips. - Lu Lu 013; Aarthy Mani; Anh Tuan Do (ISCAS, 2023)

1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing. - Bo Wang 020; Ming Ming Wong; Dongrui Li; Yi Sheng Chong; Jun Zhou 014; Weng-Fai Wong; Li-Shiuan Peh; Aarthy Mani; Mohit Upadhyay; Ananta Narayanan Balaji; Anh Tuan Do (ISCAS, 2023)

Stability Analysis of 6T SRAM at Deep Cryogenic Temperature for Quantum Computing Applications. - Seong-Beom Kim; Aarthy Mani; Leong Xu Heng Victor; Yuanjin Zheng; Anh Tuan Do (ISCAS, 2023)

Hardware-efficient Softmax Approximation for Self-Attention Networks. - Nazim Altar Koca; Anh Tuan Do; Chip-Hong Chang (ISCAS, 2023)

1V, 1.13μm pixel pitch Liquid Crystal Driver with Charge-Balancing Scheme for SLM Applications. - Aarthy Mani; Chong Yi Sheng; Di Zhu; Rasna Maruthiyodan Veetil; Moitra Parikshit; Tobias Wilhelm W. Mass; Chong Ser Choong; Xuewu Xu; Ramon José Paniagua Domínguez; Arseniy I. Kuznetsov; P. Krishna; P. Keyi; et al. (ISCAS, 2023)

A 110nW Always-on Keyword Spotting Chip using Spiking CNN in 40nm CMOS. - Chen Shen; Junran Pu; Yi Sheng Chong; Zhongyi Zhang; Wang Ling Goh; Bin Zhao; Anh Tuan Do; Yuan Gao 011 (ISCAS, 2023)

282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing. - Qibang Zang; Wang Ling Goh; Lu Lu 013; Chengshuo Yu; Junjie Mu; Tony Tae-Hyoung Kim; Bongjin Kim; Dongrui Li; Anh Tuan Do (ISCAS, 2023)

LAXOR: A Bit-Accurate BNN Accelerator with Latch-XOR Logic for Local Computing. - Dongrui Li; Tomomasa Yamasaki; Aarthy Mani; Anh Tuan Do; Niangjun Chen; Bo Wang 020 (ISLPED, 2023)

Cryogenic Characterization of 40nm CMOS for Quantum Control Applications. - Aarthy Mani; Leong Xu Heng Victor; Anh Tuan Do (ISOCC, 2023)

0.85 mW, 8-bit, 1GS/s, 58dB SFDR Cryogenic DAC for Superconducting Qubit Control Applications. - Chan Kuen Sim; Aarthy Mani; Anh Tuan Do (ISOCC, 2023)

Design of a Current Sense Amplifier with Dynamic Reference for Reliable Resistive Memory. - Byung-Kwon An; Xueyong Zhang; Anh Tuan Do; Tony Tae-Hyoung Kim (NEWCAS, 2023)

Achieving Green AI with Energy-Efficient Deep Learning Using Neuromorphic Computing. - Tao Luo 014; Weng-Fai Wong; Rick Siow Mong Goh; Anh Tuan Do; Zhixian Chen; Haizhou Li 001; Wenyu Jiang; Weiyun Yau (Commun. ACM, 2023)

A 47 TOPS/W 10T SRAM-Based Multi-Bit Signed CIM With Self-Adaptive Bias Voltage Generator for Edge Computing Applications. - Lu Lu 013; Anh-Tuan Do (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

ROC-Spin: A 28nm 2, 000 Ring-Oscillator-Collapse Spins for Solving Combinatorial Optimization Problems. - Yuqi Su; Anh Tuan Do; Tony Tae-Hyoung Kim; Bongjin Kim (A-SSCC, 2024)

A 4.2pJ/Pixel 480 fps Stereo Vision Processor with Pixel Level Pipelined Architecture and Two-Path Aggregation Semi-Global Matching. - Zehao Li; Yuncheng Lu; Anh Tuan Do; Tony Tae-Hyoung Kim (CICC, 2024)

PACE: A Scalable and Energy Efficient CGRA in a RISC-V SoC for Edge Computing Applications. - Vishnu P. Nambiar; Yi Sheng Chong; Thilini Kaushalya Bandara; Dhananjaya Wijerathne; Zhaoying Li; Rohan Juneja; Li-Shiuan Peh; Tulika Mitra; Anh Tuan Do (HCS, 2024)

High Speed SPAD Active Quenching and Reset Chipset in 55nm BCDLite Process for Quantum Applications. - Jun Zhang; Yuqi Su; Bin Zhao; Moe Thar Soe; Anh Tuan Do; Alexander Ling; Yuan Gao 011 (IEEE SENSORS, 2024)

Time-based Sensing with Linear Current-to-Time Conversion for Multi-level Resistive Memory. - Byung-Kwon An; Xueyong Zhang; Anh Tuan Do; Tony Tae-Hyoung Kim (ISCAS, 2024)

Quantum Readout Processing Accelerator with a CORDIC Core at Cryogenic Temperature. - Yi Sheng Chong; Hongyu Cao; Wang Ling Goh; Patrick Bore; Yuanzheng Paul Tan; Yung Szen Yap; Rainer Dumke; Vishnu P. Nambiar; Anh Tuan Do (ISCAS, 2024)

A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation. - Yi Sheng Chong; Rakshith Harish; Rajesh Chandrasekhara Panicker; Vishnu P. Nambiar; Anh Tuan Do (ISCAS, 2024)

Exploring Error Correction Circuits on RISC-V based Systems for Space Applications. - Nazim Altar Koca; Chip-Hong Chang; Anh Tuan Do; Vishnu P. Nambiar (ISCAS, 2024)

3881 Gbps/W, 3005 µm AES Core with State Based Clock Gating for IoT applications. - Zhangyi Pei; Vishnu P. Nambiar; Yi Sheng Chong; Wang Ling Goh; Anh Tuan Do (ISCAS, 2024)

FeCBF: A Novel Sub-Optimal Cascaded Bloom Filter Structure Based on Feature Extraction. - Quang-Manh Duong; Khoa-Sang Nguyen; Hai-Duong Nguyen; Xuan-Uoc Dao; Anh-Tuan Do; Quang-Kien Trinh (IEEE Access, 2024)

1.63 pJ/SOP Neuromorphic Processor With Integrated Partial Sum Routers for In-Network Computing. - Dongrui Li; Ming Ming Wong; Yi Sheng Chong; Jun Zhou 014; Mohit Upadhyay; Ananta Narayanan Balaji; Aarthy Mani; Weng-Fai Wong; Li-Shiuan Peh; Anh Tuan Do; Bo Wang 020 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 23.5 TOPS/W Depthwise Separable Convolution Accelerator for Event-based Depth Estimation. - Andres Brito; Tomomasa Yamasaki; Ulysse Rançon; Timothée Masquelier; Benoit R. Cottereau; Anh Tuan Do; Bo Wang 020 (ISCAS, 2025)

Accuracy-preserving Layer Normalization Approximations for Efficient Transformer Hardware Accelerators. - Nazim Altar Koca; Anh Tuan Do; Chip-Hong Chang (ISCAS, 2025)

Qubit-State Discrimination using Neural Networks with Rapid and Energy-Efficient Compute Arrays. - Yuntian Liu; Yi Sheng Chong; Benjamin Lienhard; Minghao Fan; Wang Ling Goh; Vishnu P. Nambiar; Anh Tuan Do (ISCAS, 2025)

Design and Analysis of Latch-Type Comparators for Cryogenic Operations. - Qibang Zang; Wang Ling Goh; Andres Brito; Anh Tuan Do (ISCAS, 2025)