Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit. - Bibhash Sen; Anik Sengupta; Mamata Dalui; Biplab K. Sikdar (DSD, 2010)

Enhancing the performance of HetNets via linear regression estimation of Range Expansion Bias. - Sudeepta Mishra; Anik Sengupta; C. Siva Ram Murthy (ICON, 2013)

An efficient preamble compression for multi clock-rate sampling wireless devices. - Anik Sengupta; Rahul Thakur; C. Siva Ram Murthy (ICON, 2013)

Power consumption modeling of femto-assisted cellular networks using Renewal Reward Process. - Rahul Thakur; Anik Sengupta; C. Siva Ram Murthy (ICON, 2013)

Improving capacity and energy efficiency of femtocell based cellular network through cell biasing. - Rahul Thakur; Anik Sengupta; C. Siva Ram Murthy (WiOpt, 2013)

On minimizing the system information age in vehicular ad-hoc networks via efficient scheduling and piggybacking. - Moumita Patra; Anik Sengupta; C. Siva Ram Murthy (Wirel. Networks, 2016)

A case for preamble compression in multi-clock-rate sampling devices for energy efficient idle listening. - Anik Sengupta; C. Siva Ram Murthy (Wirel. Networks, 2018)

Sewage Pooling Test for SARS-CoV-2. - Ritam Guha; Anik Sengupta; Ankan Dutta (CoRR, 2020)