High resolution digital-to-time converter for low jitter digital PLLs. - Anil Chawda; Pallavi Paliwal; Priyank Laad; Shalabh Gupta (ICECS, 2014)

A Fast Settling 4.7-5 GHz Fractional-N Digital Phase Locked Loop. - Pallavi Paliwal; Jaydip Fadadu; Anil Chawda; Shalabh Gupta (VLSID, 2016)