Parametric Performance Analysis of Synchronous and Asynchronous Heterogeneous Network on Chip. - Ayas Kanta Swain; Anil Kumar Rajput; Kamalakanta Mahapatra (iNIS, 2016)

Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard. - Neelam Arya; Anil Kumar Rajput; Manisha Pattanaik; G. K. Sharma 001 (VDAT, 2019)

Network on Chip for Consumer Electronics Devices: An Architectural and Performance Exploration of Synchronous and Asynchronous Network-on-Chip-Based Systems. - Ayas Kanta Swain; Anil Kumar Rajput; Kamala Kanta Mahapatra (IEEE Consumer Electron. Mag., 2019)

Energy Efficient 9T SRAM With R/W Margin Enhanced for beyond Von-Neumann Computation. - Anil Kumar Rajput; Manisha Pattanaik (VDAT, 2020)

Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture. - Anil Kumar Rajput; Manisha Pattanaik; Gaurav Kaushal (Microelectron. J., 2022)

An Energy-Efficient and Robust 10T SRAM Based in-Memory Computing Architecture. - Noopur Srivastava; Anil Kumar Rajput; Manisha Pattanaik; Gaurav Kaushal (VLSID, 2023)

Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation. - Anil Kumar Rajput; Manisha Pattanaik (Microelectron. J., 2023)

An Energy-Efficient Hybrid SRAM-Based In-Memory Computing Macro for Artificial Intelligence Edge Devices. - Anil Kumar Rajput; Alok Kumar Tiwari; Manisha Pattanaik (Circuits Syst. Signal Process., 2023)

BP-IMCA: An Energy-Efficient 8T SRAM-Based Bit-Parallel In-Memory Computing Architecture. - Anil Kumar Rajput; Manisha Pattanaik; Gaurav Kaushal (J. Circuits Syst. Comput., 2025)

EASM: An efficient AttnSleep model for sleep Apnea detection from EEG signals. - Madan Singh; Sujata Chauhan; Anil Kumar Rajput; Indu Verma; Alok Kumar Tiwari (Multim. Tools Appl., 2025)