A Nine-Level Inverter Topology with Equal Source Utilization. - Anilkumar Chappa; Shubhrata Gupta; Lalit Kumar Sahu; Krishna Kumar Gupta (IECON, 2020)

A Fault-Tolerant Multilevel Inverter Topology With Preserved Output Power and Voltage Levels Under Pre- and Postfault Operation. - Anilkumar Chappa; Shubhrata Gupta; Lalit Kumar Sahu; Krishna Kumar Gupta (IEEE Trans. Ind. Electron., 2021)

Fault-Tolerant Asymmetrical Multilevel Inverter With Preserved Output Power Under Post-Fault Operation. - Anilkumar Chappa; Shubhrata Gupta; Lalit Kumar Sahu; Krishna Kumar Gupta; Hani Vahedi (IEEE Trans. Ind. Electron., 2022)

Highly resilient 17-level fault-tolerant multilevel inverter topology with reduced capacitor size. - Anilkumar Chappa; Shubhrata Gupta; Lalit Kumar Sahu; Krishna Kumar Gupta; Allamsetty Hema Chander (Int. J. Circuit Theory Appl., 2024)