Non-uniform power access in large caches with low-swing wires. - Aniruddha N. Udipi; Naveen Muralimanohar; Rajeev Balasubramonian (HiPC, 2009)

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. - Niti Madan; Li Zhao 002; Naveen Muralimanohar; Aniruddha N. Udipi; Rajeev Balasubramonian; Ravishankar R. Iyer 001; Srihari Makineni; Donald Newell (HPCA, 2009)

Towards scalable, energy-efficient, bus-based on-chip networks. - Aniruddha N. Udipi; Naveen Muralimanohar; Rajeev Balasubramonian (HPCA, 2010)

Rethinking DRAM design and organization for energy-constrained multi-cores. - Aniruddha N. Udipi; Naveen Muralimanohar; Niladrish Chatterjee; Rajeev Balasubramonian; Al Davis; Norman P. Jouppi (ISCA, 2010)

Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems. - Aniruddha N. Udipi; Naveen Muralimanohar; Rajeev Balasubramonian; Al Davis; Norman P. Jouppi (ISCA, 2011)

LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems. - Aniruddha N. Udipi; Naveen Muralimanohar; Rajeev Balasubramonian; Al Davis; Norman P. Jouppi (ISCA, 2012)

Designing Efficient Memory for Future Computing Systems. - Aniruddha N. Udipi (2012)

Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device. - Manjunath Shevgoor; Jung-Sik Kim; Niladrish Chatterjee; Rajeev Balasubramonian; Al Davis; Aniruddha N. Udipi (MICRO, 2013)

Simulating DRAM controllers for future system architecture exploration. - Andreas Hansson 001; Neha Agarwal; Aasheesh Kolli; Thomas F. Wenisch; Aniruddha N. Udipi (ISPASS, 2014)

CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems. - Sagar Karandikar; Aniruddha N. Udipi; Junsun Choi; Joonho Whangbo; Jerry Zhao; Svilen Kanev; Edwin Lim; Jyrki Alakuijala; Vrishab Madduri; Yakun Sophia Shao; Borivoje Nikolic; Krste Asanovic; et al. (ISCA, 2023)