An approach to complement electronics courses using virtual environment. - Jinu Jayachandran; Nina Joseph; Maheshwar Mangat; Vinay Verma; N. P. Narendra; Aniruddha Shastri; Devendra Patil; Madhumita Date; Joseph John; Mahesh B. Patil (EDUCON, 2013)

A scheduling and binding heuristic for high-level synthesis of fault-tolerant FPGA applications. - Aniruddha Shastri; Greg Stitt; Eduardo Riccio (ASAP, 2015)

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance. - David Wilson 004; Aniruddha Shastri; Greg Stitt (Int. J. Reconfigurable Comput., 2017)