Event driven adaptively controlled explicit simulation of integrated circuits. - Anirudh Devgan; Ronald A. Rohrer (ICCAD, 1993)

ACES: A Transient Simulation Strategy for Integrated Circuits. - Anirudh Devgan; Ronald A. Rohrer (ICCD, 1993)

Adaptively controlled explicit simulation. - Anirudh Devgan; Ronald A. Rohrer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Efficient and accurate transient simulation in charge-voltage plane. - Anirudh Devgan (ICCAD, 1995)

Accurate device modeling techniques for efficient timing simulation of integrated circuits. - Anirudh Devgan (ICCD, 1995)

Efficient simulation of interconnect and mixed analog-digital circuits in ACES. - Anirudh Devgan; Ronald A. Rohrer (VLSI Design, 1995)

Transient simulation of integrated circuits in the charge-voltage plane. - Anirudh Devgan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Wire Segmenting for Improved Buffer Insertion. - Charles J. Alpert; Anirudh Devgan (DAC, 1997)

Efficient coupled noise estimation for on-chip interconnects. - Anirudh Devgan (ICCAD, 1997)

Timing analysis and optimization: from devices to systems (tutorial). - Anirudh Devgan; Leon Stok; Sandip Kundu (ICCAD, 1997)

State transformation in event driven explicit simulation. - Tuyen V. Nguyen; Anirudh Devgan (ICCAD, 1997)

Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial). - Anirudh Devgan; Sandip Kundu (ASP-DAC, 1998)

Adjoint Transient Sensitivity Computation in Piecewise Linear Simulation. - Tuyen V. Nguyen; Anirudh Devgan; Ognen J. Nastov (DAC, 1998)

Simulation of coupling capacitances using matrix partitioning. - Tuyen V. Nguyen; Anirudh Devgan; Ali Sadigh (ICCAD, 1998)

Buffer Insertion with Accurate Gate and Interconnect Delay Computation. - Charles J. Alpert; Anirudh Devgan; Stephen T. Quay (DAC, 1999)

Is wire tapering worthwhile? - Charles J. Alpert; Anirudh Devgan; Stephen T. Quay (ICCAD, 1999)

Realizable reduction for RC interconnect circuits. - Anirudh Devgan; Peter R. O'Brien (ICCAD, 1999)

Buffer insertion for noise and delay optimization. - Charles J. Alpert; Anirudh Devgan; Stephen T. Quay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K. - Anirudh Devgan; Hao Ji; Wayne Wei-Ming Dai (ICCAD, 2000)

An "Effective" Capacitance Based Delay Metric for RC Interconnect. - Chandramouli V. Kashyap; Charles J. Alpert; Anirudh Devgan (ICCAD, 2000)

A two moment RC delay metric for performance optimization. - Charles J. Alpert; Anirudh Devgan; Chandramouli V. Kashyap (ISPD, 2000)

Transient sensitivity computation in controlled explicit piecewiselinear simulation. - Tuyen V. Nguyen; Anirudh Devgan; Ognen J. Nastov; David W. Winston (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect. - Hao Ji; Anirudh Devgan; Wayne Wei-Ming Dai (ASP-DAC, 2001)

Interconnect synthesis without wire tapering. - Charles J. Alpert; Anirudh Devgan; John P. Fishburn; Stephen T. Quay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

RC delay metrics for performance optimization. - Charles J. Alpert; Anirudh Devgan; Chandramouli V. Kashyap (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

PERI: a technique for extending delay and slew metrics to ramp inputs. - Chandramouli V. Kashyap; Charles J. Alpert; Frank Liu 001; Anirudh Devgan (Timing Issues in the Specification and Synthesis of Digital Systems, 2002)

Correction to "interconnect synthesis without wire tapering". - Charles J. Alpert; Anirudh Devgan; John P. Fishburn; Stephen T. Quay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Delay and slew metrics using the lognormal distribution. - Charles J. Alpert; Frank Liu 001; Chandramouli V. Kashyap; Anirudh Devgan (DAC, 2003)

Block-based Static Timing Analysis with Uncertainty. - Anirudh Devgan; Chandramouli V. Kashyap (ICCAD, 2003)

Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics. - Jiayong Le; Lawrence T. Pileggi; Anirudh Devgan (ICCAD, 2003)

Leakage and leakage sensitivity computation for combinational circuits. - Emrah Acar; Anirudh Devgan; Rahul M. Rao; Ying Liu; Haihua Su; Sani R. Nassif; Jeffrey L. Burns (ISLPED, 2003)

Efficient techniques for gate leakage estimation. - Rahul M. Rao; Jeffrey L. Burns; Anirudh Devgan; Richard B. Brown (ISLPED, 2003)

Full chip leakage estimation considering power supply and temperature variations. - Haihua Su; Frank Liu 001; Anirudh Devgan; Emrah Acar; Sani R. Nassif (ISLPED, 2003)

Closed form expressions for extending step delay and slew metrics to ramp inputs. - Chandramouli V. Kashyap; Charles J. Alpert; Frank Liu 001; Anirudh Devgan (ISPD, 2003)

Parametric yield estimation considering leakage variability. - Rajeev R. Rao; Anirudh Devgan; David T. Blaauw; Dennis Sylvester (DAC, 2004)

Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell. - Rajiv V. Joshi; Saibal Mukhopadhyay; Donald W. Plass; Yuen H. Chan; Ching-Te Chuang; Anirudh Devgan (ESSCIRC, 2004)

Closed-form delay and slew metrics made easy. - Charles J. Alpert; Frank Liu 001; Chandramouli V. Kashyap; Anirudh Devgan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. - Chandramouli V. Kashyap; Charles J. Alpert; Frank Liu 001; Anirudh Devgan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Achieving continuous VT performance in a dual VT process. - Kanak Agarwal 001; Dennis Sylvester; David T. Blaauw; Anirudh Devgan (ASP-DAC, 2005)

Leakage power: trends, analysis and avoidance. - David T. Blaauw; Anirudh Devgan; Farid N. Najm (ASP-DAC, 2005)

Sleep transistor sizing using timing criticality and temporal currents. - Anand Ramalingam; Bin Zhang 011; Anirudh Devgan; David Z. Pan (ASP-DAC, 2005)

Spatially distributed 3D circuit models. - Michael W. Beattie; Hui Zheng; Anirudh Devgan; Byron Krauter (DAC, 2005)

An efficient algorithm for statistical minimization of total power under timing yield constraints. - Murari Mani; Anirudh Devgan; Michael Orshansky (DAC, 2005)

Variability modeling and variability-aware design in deep submicron integrated circuits. - Florentin Dartu; Anirudh Devgan; Noel Menezes (ACM Great Lakes Symposium on VLSI, 2005)

Power grid voltage integrity verification. - Maha Nizam; Farid N. Najm; Anirudh Devgan (ISLPED, 2005)

Modeling and Design of Chip-Package Interface. - Anirudh Devgan; Luca Daniel; Byron Krauter; Lei He 001 (ISQED, 2005)

Design of sub-90nm Circuits and Design Methodologies. - Anirudh Devgan; Ruchir Puri; Sachin Sapatnaker; Tanay Karnik; Rajiv V. Joshi (ISQED, 2005)

Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. - Rahul M. Rao; Kanak Agarwal 001; Anirudh Devgan; Kevin J. Nowka; Dennis Sylvester; Richard B. Brown (ISQED, 2005)

Power Variability and Its Impact on Design. - Anirudh Devgan; Sani R. Nassif (VLSI Design, 2005)

Modeling and Analysis of Parametric Yield under Power and Performance Constraints. - Rajeev R. Rao; David T. Blaauw; Dennis Sylvester; Anirudh Devgan (IEEE Des. Test Comput., 2005)

Leakage and Leakage Sensitivity Computation for Combinational Circuits. - Emrah Acar; Anirudh Devgan; Sani R. Nassif (J. Low Power Electron., 2005)

Robust analytical gate delay modeling for low voltage circuits. - Anand Ramalingam; Sreekumar V. Kodakara; Anirudh Devgan; David Z. Pan (ASP-DAC, 2006)

Analytical yield prediction considering leakage/performance correlation. - Rajeev R. Rao; Anirudh Devgan; David T. Blaauw; Dennis Sylvester (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce. - Anand Ramalingam; Anirudh Devgan; David Z. Pan (J. Low Power Electron., 2007)

A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits. - Murari Mani; Anirudh Devgan; Michael Orshansky; Yaping Zhan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Reinventing EDA with manycore processors. - Sachin S. Sapatnekar; Eshel Haritan; Kurt Keutzer; Anirudh Devgan; Desmond Kirkpatrick; Stephen Meier; Duaine Pryor; Tom Spyrou (DAC, 2008)

Accelerated design of analog, mixed-signal circuits in Titan. - Anirudh Devgan; Bülent Basaran; David Colleran; Mar Hershenson (ISPD, 2009)