Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded Memory. - Anirudh Iyengar; Swaroop Ghosh (DAC, 2014)

DWM-PUF: A low-overhead, memory-based security primitive. - Anirudh Iyengar; Kenneth Ramclam; Swaroop Ghosh (HOST, 2014)

Synergistic circuit and system design for energy-efficient and robust domain wall caches. - Seyedhamidreza Motaman; Anirudh Iyengar; Swaroop Ghosh (ISLPED, 2014)

Threshold Voltage-Defined Switches for Programmable Gates. - Anirudh Iyengar; Swaroop Ghosh (CoRR, 2015)

Domain Wall Magnets for Embedded Memory and Hardware Security. - Anirudh Srikant Iyengar; Swaroop Ghosh; Kenneth Ramclam (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

MTJ-Based State Retentive Flip-Flop With Enhanced-Scan Capability to Sustain Sudden Power Failure. - Anirudh Srikant Iyengar; Swaroop Ghosh; Jae-Won Jang (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Data privacy in non-volatile cache: Challenges, attack models and solutions. - Nitin Rathi; Swaroop Ghosh; Anirudh Iyengar; Helia Naeimi (ASP-DAC, 2016)

Side channel attacks on STTRAM and low-overhead countermeasures. - Anirudh Iyengar; Swaroop Ghosh; Nitin Rathi; Helia Naeimi (DFT, 2016)

A novel threshold voltage defined switch for circuit camouflaging. - Ithihasa Reddy Nirmala; Deepak Vontela; Swaroop Ghosh; Anirudh Iyengar (ETS, 2016)

Retention Testing Methodology for STTRAM. - Anirudh Iyengar; Swaroop Ghosh; Srikant Srinivasan (IEEE Des. Test, 2016)

Overview of Circuits, Systems, and Applications of Spintronics. - Swaroop Ghosh; Anirudh Iyengar; Seyedhamidreza Motaman; Rekha Govindaraj; Jae-Won Jang; Jinil Chung; Jongsun Park 001; Xin Li 001; Rajiv V. Joshi; Dinesh Somasekhar (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Spintronic PUFs for Security, Trust, and Authentication. - Anirudh Iyengar; Swaroop Ghosh; Kenneth Ramclam; Jae-Won Jang; Cheng-Wei Lin (ACM J. Emerg. Technol. Comput. Syst., 2016)

Novel magnetic burn-in for retention testing of STTRAM. - Mohammad Nasim Imtiaz Khan; Anirudh Srikant Iyengar; Swaroop Ghosh (DATE, 2017)

CTCG: Charge-trap based camouflaged gates for reverse engineering prevention. - Asmit De; Anirudh Iyengar; Mohammad Nasim Imtiaz Khan; Sung-Hao Lin; Sandeep Krishna Thirumala; Swaroop Ghosh; Sumeet Kumar Gupta (HOST, 2018)

Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection. - Anirudh Srikant Iyengar; Deepak Vontela; Ithihasa Reddy Nirmala; Swaroop Ghosh; Seyedhamidreza Motaman; Jae-Won Jang (ISLPED, 2018)

Magnetic Tunnel Junction Reliability Assessment Under Process Variations and Activity Factors and Mitigation Techniques. - Anirudh Srikant Iyengar; Swaroop Ghosh; Nitin Rathi (J. Low Power Electron., 2018)

Novel Magnetic Burn-In for Retention and Magnetic Tolerance Testing of STTRAM. - Mohammad Nasim Imtiaz Khan; Anirudh Iyengar; Swaroop Ghosh (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Threshold-Defined Logic and Interconnect for Protection Against Reverse Engineering. - Jae-Won Jang; Asmit De; Deepak Vontela; Ithihasa Reddy Nirmala; Swaroop Ghosh; Anirudh Iyengar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A Reference-less Slope Detection Technique in 65nm for Robust Sensing of 1T1R Arrays. - Seyedhamidreza Motaman; Swaroop Ghosh; Jae-Won Jang; Anirudh Iyengar; Rekha Govindaraj; Zakir Khondker (CoRR, 2023)