Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell. - Anis Feki; Bruno Allard; David Turgis; Jean-Christophe Lafont; Lorenzo Ciampolini (ISOCC, 2012)

Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI. - Fady Abouzeid; Audrey Bienfait; Kaya Can Akyel; Anis Feki; Sylvain Clerc; Lorenzo Ciampolini; Fabien Giner; Robin Wilson; Philippe Roche (IEEE J. Solid State Circuits, 2014)