A Method for Integrating Network-on-Chip Topologies with 3D ICs. - M. Pawan Kumar; Anish S. Kumar; Srinivasan Murali; Luca Benini; Kamakoti Veezhinathan (ISVLSI, 2011)

A Simulation Based Buffer Sizing Algorithm for Network on Chips. - Anish S. Kumar; M. Pawan Kumar; Srinivasan Murali; V. Kamakoti 001; Luca Benini; Giovanni De Micheli (ISVLSI, 2011)

A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands. - Anish S. Kumar; M. Pawan Kumar; Srinivasan Murali; V. Kamakoti 001; Luca Benini; Giovanni De Micheli (J. Electr. Comput. Eng., 2012)