PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch. - Pieter Schuddinck; Fabian M. Bufler; Yang Xiang; Anita Farokhnejad; Gioele Mirabelli; Anne Vandooren; Bilal Chehab; A. Gupta; César Roda Neve; Geert Hellings; Julien Ryckaert (VLSI Technology and Circuits, 2022)

Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. - Giuliano Sisto; R. Preston; Rongmei Chen; Gioele Mirabelli; Anita Farokhnejad; Yun Zhou; Ivan Ciofi; Anne Jourdain; A. Veloso; Michele Stucchi; Odysseas Zografos; Pieter Weckx; et al. (VLSI Technology and Circuits, 2023)

Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits. - Yun Zhou; S. C. Song; Halil Kükner; Giuliano Sisto; Sheng Yang; Anita Farokhnejad; Mohamed Naeim; Moritz Brunion; Ji-Yung Lin; Odysseas Zografos; Pieter Weckx; Shashank Ekbote; et al. (VLSI Technology and Circuits, 2024)

InterA-ECC: Interconnect-Aware Error Correction in STT-MRAM. - Surendra Hemaram; Mahta Mayahinia; Mehdi B. Tahoori; Francky Catthoor; Siddharth Rao; Sebastien Couet; Tommaso Marinelli; Anita Farokhnejad; Gouri Sankar Kar (DATE, 2025)

Live Demonstration: N2 Nanosheet Pathfinding-PDK. - Chaohan Wang; Jack Cousins; Anita Farokhnejad; Marie Garcia Bardon; Julien Ryckaert (ISCAS, 2025)