Power and Performance Tabu Search Based Multicore Network-on-Chip Design. - Anita Tino; Gul N. Khan (ICPP Workshops, 2010)

Multi-objective Tabu Search based topology generation technique for application-specific Network-on-Chip architectures. - Anita Tino; Gul N. Khan (DATE, 2011)

Wireless vibrotactile feedback system for postural response improvement. - Anita Tino; Melanie Carvalho; Nelson F. Preto; Kristiina M. Valter McConville (EMBC, 2011)

Designing power and performance optimal application-specific Network-on-Chip architectures. - Anita Tino; Gul N. Khan (Microprocess. Microsystems, 2011)

Synthesis of NoC Interconnects for Multi-core Architectures. - Gul N. Khan; Anita Tino (CISIS, 2012)

Synthesis of NoC Interconnects for Custom MPSoC Architectures. - Gul N. Khan; Anita Tino (NOCS, 2012)

Hardware realization of GALS based cortical column systems. - Anita Tino; Gul N. Khan; Fei Yuan 005 (AHS, 2013)

Towards Hardware Realizations of Intelligent Systems: A Cortical Column Approach. - Anita Tino; Gul N. Khan; Fei Yuan 005 (ICPP, 2013)

High performance NoC synthesis using analytical modeling and simulation with optimal power and minimal IC area. - Anita Tino; Gul N. Khan (J. Syst. Archit., 2013)

Addressing processor back-end issues with RCUs. - Anita Tino; Kaamran Raahemifar (AHS, 2015)

Towards Multicore Performance with Configurable Computing Units. - Anita Tino; Kaamran Raahemifar (ARCS, 2016)

Assessing Multi-task Placement Algorithms in RCUs. - Anita Tino; Kaamran Raahemifar (IPDPS Workshops, 2016)

Increasing the efficiency and feasibility of configurable computing units. - Anita Tino; Kaamran Raahemifar (J. Syst. Archit., 2017)

SIMT-X: Extending Single-Instruction Multi-Threading to Out-of-Order Cores. - Anita Tino; Caroline Collange; André Seznec (ACM Trans. Archit. Code Optim., 2020)