The Evolution of Channelization Receiver Architecture: Principles and Design Challenges. - Jusung Kim; Dzuhri Radityo Utomo; Anjana Dissanayake; Seok-Kyun Han; Sang-Gug Lee 001 (IEEE Access, 2017)

A 2.4GHz, -102dBm-sensitivity, 25kb/s, 0.466mW interference resistant BFSK multi-channel sliding-IF ULP receiver. - Oh-Yong Jung; Hyun-Gi Seok; Anjana Dissanayake; Sang-Gug Lee 001 (ASP-DAC, 2018)

A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-up Time. - Ningxi Liu; Rishika Agarwala; Anjana Dissanayake; Daniel S. Truesdell; Sumanth Kamineni; Xing Chen 004; David D. Wentzloff; Benton H. Calhoun (ESSCIRC, 2018)

A 45-µW, 162.1-dBc/Hz FoM, 490-MHz Two-Stage Differential Ring VCO Without a Cross-Coupled Latch. - Oh-Yong Jung; Hyun-Gi Seok; Anjana Dissanayake; Sang-Gug Lee 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver. - Jesse Moody; Anjana Dissanayake; Henry L. Bishop; Ruochen Lu; Ningxi Liu; Divya Duvvuri; Anming Gao; Daniel S. Truesdell; N. Scott Barker; Songbin Gong; Benton H. Calhoun; Steven M. Bowers (VLSI Circuits, 2019)

A 2.5 ppm/°C 1.05-MHz Relaxation Oscillator With Dynamic Frequency-Error Compensation and Fast Start-Up Time. - Ningxi Liu; Rishika Agarwala; Anjana Dissanayake; Daniel S. Truesdell; Sumanth Kamineni; Benton H. Calhoun (IEEE J. Solid State Circuits, 2019)

A- 108dBm Sensitivity, -28dB SIR, 130nW to 41µW, Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiver. - Anjana Dissanayake; Jesse Moody; Henry L. Bishop; Daniel S. Truesdell; Henry Muhlbauer; Ruochen Lu; Anming Gao; Songbin Gong; Benton H. Calhoun; Steven M. Bowers (CICC, 2020)

A Multichannel, MEMS-Less -99dBm 260nW Bit-Level Duty Cycled Wakeup Receiver. - Anjana Dissanayake; Henry L. Bishop; Jesse Moody; Henry Muhlbauer; Benton H. Calhoun; Steven M. Bowers (VLSI Circuits, 2020)

A 785nW Multimodal (V/I/R) Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring. - Peng Wang 166; Rishika Agarwala; Henry L. Bishop; Anjana Dissanayake; Benton H. Calhoun (VLSI Circuits, 2020)

Stacked Transconductance Boosting for Ultra-Low Power 2.4GHz RF Front-End Design. - Anjana Dissanayake; Steven M. Bowers; Benton H. Calhoun (ISCAS, 2021)

21.5 An Integrated 2.4GHz -91.5dBm-Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver Achieving 2μ W at 100ms Latency. - Henry L. Bishop; Anjana Dissanayake; Steven M. Bowers; Benton H. Calhoun (ISSCC, 2021)

A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring. - Rishika Agarwala; Peng Wang 166; Henry L. Bishop; Anjana Dissanayake; Benton H. Calhoun (IEEE J. Solid State Circuits, 2021)

A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver. - Anjana Dissanayake; Henry L. Bishop; Steven M. Bowers; Benton H. Calhoun (IEEE J. Solid State Circuits, 2022)

A -102dBm Sensitivity, 2.2μA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR. - Linsheng Zhang; Divya Duvvuri; Suprio Bhattacharya; Anjana Dissanayake; Xinjian Liu; Henry L. Bishop; Yaobin Zhang; Travis N. Blalock; Benton H. Calhoun; Steven M. Bowers (CICC, 2023)

23.2 A 1mm2 Software-Defined Dual-Mode Bluetooth Transceiver with 10dBm Maximum TX Power and -98.2dBm Sensitivity 2.96mW RX Power at 1Mb/s. - Nicola Scolari; Franz-Xaver Pengg; Konstantinos Manetakis; Camilo A. Salazar; Alexandre Vouilloz; Ernesto Pérez Serna; Anjana Dissanayake; Pascal Persechini; Vladimir Kopta; Erwan Le Roux; Francesco Chicco; Stefano Cillo; et al. (ISSCC, 2024)

MenTeR: A fully-automated Multi-agenT workflow for end-to-end RF/Analog Circuits Netlist Design. - Pin-Han Chen; Yu-Sheng Lin; Wei-Cheng Lee; Tin-Yu Leu; Po-Hsiang Hsu; Anjana Dissanayake; Sungjin Oh; Chinq-Shiun Chiu (CoRR, 2025)